Rohm Co., Ltd.

Maiko Hatano

Takukazu Otsuka

Katsuhiko Yoshihara

Seita Iwahashi

Ryuta Watanabe

Hirotaka Otake

Tatsuya Miyazaki

The power semiconductor apparatus includes: a semiconductor device; a bonding layer on chipdisposed on an upper surface of the semiconductor device; and a metal leaddisposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal leadhas a three-laminated structure including: a second metal layerhaving a CTE equal to or less than 5×10/° C., for example; and a first metal layerand a third metal layersandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.

Power semiconductor apparatus and fabrication method for the same

A semiconductor device Aincludes a semiconductor elementA having an element obverse faceand an element reverse face, the element obverse facehaving an obverse face electrodeformed thereon and the element reverse facehaving a reverse face electrodeformed thereon, a conductive substrateA including an obverse faceA opposed to the element reverse face, and to which the reverse face electrodeis conductively bonded, a conductive substrateB including an obverse faceB and spaced from the conductive substrateA in a width direction x, and a lead memberextending in the width direction x, and electrically connecting the obverse face electrodeand the conductive substrateB. The lead memberis located ahead of the obverse faceB in the direction in which the obverse faceB is oriented, and bonded to the obverse face electrodevia a lead bonding layer. The conductive substrateA, the semiconductor elementA, and the lead bonding layeroverlap with the conductive substrateB, as viewed in the width direction x.

Semiconductor device and method for manufacturing semiconductor device

A power module (PM) includes: an insulating substrate; a semiconductor device disposed on the insulating substrate, the semiconductor device including electrodes on a front surface side and a back surface side thereof; and a graphite plate having an anisotropic thermal conductivity, the graphite plate of which one end is connected to the front surface side of the semiconductor device and the other end is connected to the insulating substrate, wherein heat of the front surface side of the semiconductor device is transferred to the insulating substrate through the graphite plate. There is provide an inexpensive power module capable of reducing a stress and capable of exhibiting cooling performance not inferior to that of the double-sided cooling structures.

Power module and fabrication method of the same, graphite plate, and power supply equipment

A semiconductor device includes an insulating substrate, a first and a second obverse-surface metal layers disposed on an obverse surface of the insulating substrate, a first and a second reverse-surface metal layers disposed on a reverse surface of the insulating substrate, a first conductive layer and a first semiconductor element disposed on the first obverse-surface metal layer, and a second conductive layer and a second semiconductor element disposed on the second obverse-surface metal layer. Each of the first conductive layer and the second conductive layer has an anisotropic coefficient of linear expansion and is arranged such that the direction in which the coefficient of linear expansion is relatively large is along a predetermined direction perpendicular to the thickness direction of the insulating substrate. The first and second reverse-surface metal layers are smaller than the first and second obverse-surface metal layers in dimension in the predetermined direction.

Semiconductor device

A semiconductor device Aincludes a semiconductor elementA having an element obverse faceand an element reverse facethe element obverse facehaving an obverse face electrodeformed thereon and the element reverse facehaving a reverse face electrodeformed thereon, a conductive substrateA including an obverse faceA opposed to the element reverse faceand to which the reverse face electrodeis conductively bonded, a conductive substrateB including an obverse faceB and spaced from the conductive substrateA in a width direction x, and a lead memberextending in the width direction x, and electrically connecting the obverse face electrodeand the conductive substrateB. The lead memberis located ahead of the obverse faceB in the direction in which the obverse faceB is oriented, and bonded to the obverse face electrodevia a lead bonding layerThe conductive substrateA, the semiconductor elementA, and the lead bonding layeroverlap with the conductive substrateB, as viewed in the width direction x.

Semiconductor device with connecting member for electrode and method of manufacturing

The power semiconductor apparatus includes: a semiconductor device; a bonding layer on chipdisposed on an upper surface of the semiconductor device; and a metal leaddisposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal leadhas a three-laminated structure including: a second metal layerhaving a CTE equal to or less than 5&#xd7;10/&#xb0; C., for example; and a first metal layerand a third metal layersandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.

A power module includes: a plate-shaped thick copper substrate, a conductive stress relaxation metal layer disposed on the thick copper substrate, a semiconductor device disposed on the stress relaxation metal layer, and a plated layer disposed on the stress relaxation metal layer, wherein the semiconductor device is bonded to the stress relaxation metal layer via the plated layer. The thick copper substrate includes a first thick copper layer and a second thick copper layer disposed on the first thick copper layer, and the stress relaxation metal layer is disposed on the second thick copper layer. A part of the semiconductor device is embedded to be fixed to the stress relaxation metal layer. A bonded surface between the semiconductor device and the stress relaxation metal layer are integrated to each other by means of diffusion bonding or solid phase diffusion bonding.

Growing community of inventors

Kyoto, Japan

Maiko Hatano