Globalfoundries Inc.

Qimonda Ag

Infineon Technologies Ag

Rising Silicon, Inc.

Maik Liebau

Eugen Unger

Georg Duesberg

Matthias Lehr

Franz Kreupl

Dirk Breuer

Georg Stefan Dusberg

Olaf Storbeck

Andrew Graham

Ronny Pfuetzner

Christian Kapteyn

Guenther Aichmayr

Thomas Betzl

A semiconductor device includes a metallization system positioned above a substrate and a die seal positioned at least in the metallization system and delimiting a die region. The die seal includes a via line feature having an axial length and including one or more first portions having a first target dimension and one or more second portions along the axial length. The one or more second portions have a second target dimension less than the first target dimension.

Semiconductor device comprising a die seal including long via lines

The patterning technique used for forming sophisticated metallization systems of semiconductor devices may be monitored and evaluated more efficiently by incorporating at least one via line feature into the die seal. In this manner, high statistical significance may be obtained compared to conventional strategies, in which the respective test structures for evaluating patterning processes may be provided at specific sites in the frame region and/or die region. Moreover, by providing a 'long' via line feature, superior sensitivity for variations of depth of focus may be achieved.

A method comprises forming a first layer of an electrically insulating material over a semiconductor structure. A recess is formed in the first layer of electrically insulating material. A capacitor layer stack is deposited over the first layer of electrically insulating material. The capacitor layer stack includes one or more bottom electrode layers, a dielectric layer and a top electrode layer, wherein a first portion of the capacitor layer stack is arranged in the recess and a second portion of the capacitor layer stack is arranged over a portion of the first layer of electrically insulating material adjacent the recess. A chemical mechanical polishing process is performed. The chemical mechanical polishing process removes the second portion of the capacitor layer stack, wherein the first portion of the capacitor layer stack is not removed.

Method of forming a semiconductor structure including a metal-insulator-metal capacitor

One embodiment of the present invention provides a method for the deposition of a Carbon containing layer on a Silicon surface wherein a (i) substantially Silicon-oxide-free or reduced oxide interface results between Silicon and the Carbon containing layer during the deposition. In another embodiment, the present invention provides a method for deposition of a Carbon containing layer wherein the deposition process is substantially soot (particle)-free or reduction of soot.

Methods for elimination or reduction of oxide and/or soot deposition in carbon containing layers

A method of making an integrated circuit comprises providing a substrate and forming a structure on the substrate comprising a first enclosed portion of a carbon material and a second portion of the carbon material, wherein an intersection of the first and second portion of the carbon material has a defined dimension. The method further comprises processing the substrate with a plasma comprising hydrogen in order to etch the second portion of the carbon material, wherein the defined dimension of the intersection of the first and second portion of the carbon material substantially suppresses etching of the first enclosed portion of the carbon material in a self-limiting way.

Integrated circuits, micromechanical devices, and method of making same

In a method of producing a layer arrangement, a substantially carbon-comprising, electrically conductive carbon layer is formed. A protective layer is formed on the carbon layer. An electrically insulating layer is formed on the protective layer, the protective layer protecting the carbon layer from damage during the formation of the electrically insulating layer. Furthermore, a layer arrangement is provided, having a substantially carbon-comprising, electrically conductive carbon layer, a protective layer formed on the carbon layer, and an electrically insulating layer formed on the protective layer, the protective layer being used to avoid damage to the carbon layer by the electrically insulating layer.

Method of producing a layer arrangement, method of producing an electrical component, layer arrangement, and electrical component

A process for silanizing carbon nanotubes, wherein the carbon nanotubes are oxidized and subsequently exposed to a saturated gas phase including one or more organosilane derivatives which form covalent bonds to the carbon nanotubes with siloxane formation.

Silanized carbon nanotubes and method for the production thereof

A process for producing a nanoelement arrangement and to a nanoelement arrangement. A first nanoelement is at least partially covered with catalyst material for catalyzing the growth of nanoelements. Furthermore, at least one second nanoelement is grown on the catalyst material. Also, a nanoelement arrangement having a first nanoelement on which at least one predetermined region is covered with catalyst material for catalyzing the growth of nanoelements, and at least one second nanoelement grown on the catalyst material.

Process for producing a nanoelement arrangement, and nanoelement arrangement

A method for targeted deposition of a nanotube on a planar surface includes providing a ram made from elastomeric material and having a relief structure on its surface. A microfluid capillary system, with an inlet and an outlet, is then formed by applying the ram to a planar substrate. A dispersion of nanotubes is brought into contact with the inlet, thereby enabling capillary force to disperse the nanotubes. through the microfluid capillary system. The resulting dispersion of nanotubes is then dried and the ram removed.

Growing community of inventors

Dresden, Germany

Maik Liebau