Western Digital Technologies, Inc.

Sandisk Technologies Inc.

Sandisk Il Ltd.

Mahmud Asfur

Mordekhay Zehavi

Yonatan Tzafrir

Israel Zimmerman

Shahar Bar-Or

Eyal Sobol

Yuri Ryabinin

Yigal Eli

Alex Lemberg

Or Faerman

Rustam Freidel

Yossef Tamir

Various devices, such as storage devices or systems are configured to transmit data between various components over one or more interfaces. The operation of these interfaces is based on the mechanical limits of the components doing the communication, often latches. Latches often require a setup and hold time limit on the signal being transmitted to be held a desired value. Because the physical effects of the environment, such as voltage being provided, temperature of the component, for example, can affect the operation of the latch, there is often a large margin used to operate them. These large margins avoid errors but decrease overall speed of the interface. By utilizing a test latch within an interface bus group with a drop in operating voltage, changes in output detected can be indicative of upcoming errors. Once detected, the error can be remedied by increasing voltage, lowering operating speeds, or cooling the components.

Interface bus speed optimization

Various apparatuses, systems, methods, and media are disclosed to provide wired communication interface with common mode voltage adjustment for high bit rate communication between devices. In one example, a high speed data communication interface can split the input signal into a high frequency component and a low frequency component. The high speed data communication interface can adjust the common mode voltage using the low frequency component and combine the high frequency component and the low frequency component by superposition after adjusting the common mode voltage.

High bit rate communication interface with common mode voltage adjustment

A method and apparatus for the increase of internal data throughput and processing capability for SSD's, to enable processing of database commands on an SSD. A front-end ASIC is provided with 256 to 512 RISC processing cores to enable decomposition and parallelization of host commands to front-end module (FM) ASICs that each in turn are coupled to multiple NVM dies, as well as processing of host database operations such as insert, select, update, and delete. Each FM ASIC is architected to increase parity bits to 33.3% of NVM data, and process parity data with 14 LDPC's. By increasing the parity bits to 33.3%, BER is reduced, power consumption is reduced, and data throughput within the SSD is increased.

High throughput, low power, high parity architecture for database SSD

A data storage device includes a controller and a memory. The controller includes a host interface and a memory interface. The controller performs a first operation on the memory through the memory interface at a first frequency associated with the host interface to determine a first data pattern. The controller performs a read operation on the memory through the memory interface at a second frequency to determine a second data pattern. The controller changes the first frequency by a predetermined amount until the first frequency is equal to a maximum operating frequency having an associated risk of a setup/hold violation that is below a predetermined probability.

Method for maximizing frequency while checking data integrity on a physical interface bus

A data storage device includes a controller and a memory. The controller includes a host interface and a memory interface. The controller writes a first data test to a memory device through either the host interface or the memory interface at a first voltage level to determine a first write value. The controller reads the first data test written to the memory device through the same interface, either the host interface or the memory interface, at a second voltage level to determine a first read value. The controller then changes the second voltage to a third voltage based on a determination of whether the first read value is equal to the first write value to dynamically alter a working voltage level of the storage device in response to changing process, voltage, and temperature conditions.

Method for maximizing power efficiency in memory interface block

A device includes a first latch configured to be coupled to a bus and configured to receive a data signal and a clock signal. The device also includes a delay element configured to generate a delayed version of the data signal or a delayed version of the clock signal. A second latch is coupled to the delay element and configured to receive the delayed version of the data signal or the delayed version of the clock signal. The device further includes a comparator coupled to the first latch and the second latch. The comparator is configured to receive a first output from the first latch and a second output from the second latch.

Systems and methods of adjusting an interface bus speed

A storage device may be configured to adjust a frequency of a clock signal. The clock signal may be associated with a data transfer rate of data to be communicated between a controller and a memory of the storage device. In some implementations, the frequency maybe adjusted responsive to at least one of a supply voltage provided to the storage device, a temperature of the storage device, or a physical characteristic of the storage device.

Data transfer rate adjustment

Methods and systems are provided where a memory controller for non-volatile memory transfers data to and from random access memory over a second double data rate bus, and a host system access the random access memory over a first double data rate bus. The memory controller may transfer the data in response to a command received by the memory controller from a host system via a block storage protocol bus. Alternatively or in addition, the memory controller may transfer the data as part of caching data internal to the non-volatile memory.

Block storage protocol to RAM bypass

Methods, systems, and computer readable media for providing BIOS data and non-BIOS data on the same non-volatile memory. According to one aspect, a system for providing BIOS data and non-BIOS data on the same non-volatile memory includes a controller for controlling access by a host to a non-volatile memory for storing data, the data including BIOS data and non-BIOS data. The controller includes a first bus interface for communicating data to and from the host via a first bus of a first bus protocol, a second bus interface for communicating data to and from the host via a second bus of a second bus protocol, and a third interface for communicating data to and from the non-volatile memory. The first bus comprises a bus that is operable after power-on reset and before BIOS is accessed.

Methods, systems, and computer readable media for providing basic input/output system (BIOS) data and non-BIOS data on the same non-volatile memory

Programmer's data is initially stored in a memory device of the storage device by using an MBC storage scheme. After the storage device is embedded in a host device, the programmer's data is internally read from the memory device by using conventional read reference voltages, and the number of erroneous data bits in the programmer's data is calculated. If the programmer's data includes an uncorrectable number of erroneous data bits, the programmer's data is iteratively reread by using unconventional read reference voltages with decreased levels. The iteration process, which includes decreasing the level of the read reference voltages and recalculating the number of erroneous data bits, is terminated when the number of erroneous data bits in the programmer's is less than or equals a predetermined number of erroneous data bits, after which the storage device restores the programmer's data and conventionally rewrites it into the memory device.

Preloading data into a flash storage device

A card adapter includes a first memory card interface configured to be connected to a first memory card. The first memory card is associated with a first file system. The card adapter includes a second memory card interface that is configured to be connected to a second memory card. The second memory card is associated with a second file system. The card adapter also includes a host interface configured to connect to a host. The card adapter includes a controller operatively interposed between the first and second memory card interfaces and the host interface. The controller is configured to control the first memory card interface and the second memory card interface to control connections between each memory card that is connected thereto with the host. The controller is also configured to operate in each of two selectable modes. In a first mode the controller is operative to emulate a virtual file system that presents to the host the first file system and the second file system as a unified image. In a second mode, the controller presents to the host either the first file system of the first memory card connected to the first memory card interface or the second file system of the second memory card connected to the second memory card interface. The card adapter also includes a mode switch coupled to the controller and configured to receive a user selection of one of the two selectable modes.

Growing community of inventors

Bat Yam, Israel

Mahmud Asfur