Avalanche Technology, Inc.

Cirrus Logic Inc.

Mahmood Mozaffari

Ebrahim Abedifard

Yuchen Zhou

Petro Estakhri

Parviz Keshtbod

Yiming Huai

Siamack Nemazie

Mahmud M Assar

Kimihiro Satoh

Bing K Yen

A spin-transfer torque magnetic random access memory (STTMRAM) cell is disclosed. The memory cell comprises a selected magnetic tunnel junction (MTJ) identified to be programmed; a first transistor having a first port, a second port and a gate, the first port of the first transistor coupled to the selected MTJ; a first neighboring MTJ coupled to the selected MTJ through the second port of the first transistor; a second transistor having a first port, a second port, and a gate, the first port of the second transistor coupled to the selected MTJ; a second neighboring MTJ coupled to the selected MTJ through the second port of the second transistor; a first bit/source line coupled to the second end of the selected MTJ; and a second bit/source line coupled to the second end of the first neighboring MTJ and the second end of the second neighboring MTJ.

Spin-transfer torque magnetic random access memory (STTMRAM) with enhanced write current

A method of writing to a magneto tunnel junction (MTJ) includes writing data to the MTJ, reading the written data using a first reference MTJ and reading the written data using a second reference MTJ. Based on the reading steps and the result of the comparing step, setting a select bit to select the proper reference for future reads.

Method of sensing data in magnetic random access memory with overlap of high and low resistance distributions

The present invention is directed to a method for reading and writing an STT-MRAM multi-level cell (MLC), which includes a plurality of MTJ memory elements coupled in series. The method detects the resistance states of individual MTJ memory elements in an MLC by sequentially writing each memory element to the low resistance state in order of ascending parallelizing write current threshold. If a written element switches the resistance state thereof after the write step, then the written element was in the high resistance state prior to the write step. Otherwise, the written element was in the low resistance state prior to the write step. The switching of the resistance state can be ascertained by comparing the resistance or voltage values of the plurality of memory elements before and after writing each of the plurality of memory elements in accordance with the embodiments of the present invention.

Method for reading and writing multi-level cells

A semiconductor mass storage device can be substituted for a rotating hard disk. The device avoid an erase cycle each time information stored in the mass storage is changed. Erase cycles are avoided by programming an altered data file into an empty mass storage block rather than over itself as a hard disk would. Periodically, the mass storage will need to be cleaned up. Secondly, a circuit and method are provided for evenly using all blocks in the mass storage. These advantages are achieved through the use of several flags, a map to correlate a logical address of a block to a physical address of that block and a count register for each block. In particular, flags are provided for defective blocks, used blocks, old versions of a block, a count to determine the number of times a block has been erased and written and an erase inhibit flag. Reading is performed by providing the logical block address to the memory storage. The system sequentially compares the stored logical block addresses until it finds a match. That data file is then coupled to the system.

Flash memory mass storage architecture incorporating wear leveling

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Los Gatos, CA, United States of America

Mahmood Mozaffari