Sambanova Systems, Inc.

Mahmood Khayatzadeh

Jin-uk Shin

Fahim Ur Rahman

Zuxu Qin

Jinuk Shin

Satyajit Sarkar

A timing margin sensor circuit includes one or more time-to-digital converters (TDCs), a predictor, and a translation circuit. The TDC(s) measure(s) progress of a clock signal through one or more chains of delay stages. The progress depends on sense conditions acting upon the delay chain, such as the supply voltage and the temperature. The predictor receives the measured progress. If the delay chain becomes slower, the predictor extrapolates a predicted progress value. If the delay chain becomes faster, the predictor outputs the actual progress value. The translator translates the predictor output value to sense information that can be used in a clock stretcher circuit. The timing margin sensor may further have an averager/selector to average or select from the results of multiple TDCs. The timing margin sensor may further have a calibrator to compensate for nominal sense conditions, and one or more tunable delays circuits.

Timing margin sensor

A clock stretcher includes a delay line, a control unit, and a combiner. The delay line outputs a series of delayed phases of an input clock. The control circuit is clocked by the input clock. It outputs a series of delayed phase enable signals. The combiner circuit receives the delayed phases from the delay line and the delayed phase enable signals from the control circuit, and outputs a modified clock. The control circuit determines if stretching has started, if wraparound must occur, and if a next phase must be enabled. The combiner retimes a delayed phase enable signal for a first delayed phase using a flipflop clocked by a second delayed phase to generate a retimed phase enable signal. The combiner uses the retimed phase enable signal to pass a pulse of the first delayed phase to the output as a pulse of the modified clock.

Variable-length clock stretcher with combiner timing logic

A clock stretcher includes a DLL that derives delayed versions of an input clock signal, and a combiner that cyclically selects the delayed versions to generate a modified clock signal. The DLL has a phase error because of its finite bandwidth. The clock stretcher measures the phase error and corrects for a glitch in the modified clock signal by using the phase error when phase selection wraparound occurs. The clock stretcher may operate from a power supply that has droops, without intervening voltage regulation.

Variable-length clock stretcher with correction for glitches due to finite DLL bandwidth

A clock stretcher includes a DLL that derives delayed versions of an input clock signal. The clock stretcher has passive and stretching modes. It operates from a sensed power supply without intervening voltage regulation. In passive mode, it forwards input clock pulses to the clock stretcher output. The input clock pulses are delayed by fewer than 10 DLL delay line delay stages. In stretching mode, a combiner cyclically selects the delayed versions of the input clock signal to generate a modified clock signal. The combiner uses a hop code, dependent on a sensed condition, to determine the step size for the cyclical selection. To enter passive mode, the clock stretcher tests if a passive mode entry threshold is met. The threshold includes two conditions: the hop code must be zero, and phase selection must have reached a wraparound point that may have been corrected for a delay line offset.

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Belmont, CA, United States of America

Mahmood Khayatzadeh