Mentor Graphics Corporation

Calypto Design Systems, Inc.

Maheshinder Goyal

Peter Pius Gutberlet

Bryan Darrell Bowyer

Andres Rafael Takach

Pankaj P Chauhan

Saurabh Jain

Sameer Kapoor

Gagandeep Singh

Kunal Bindal

Disclosed herein are representative embodiments of methods, apparatus, and systems for performing formal verification of circuit descriptions. In certain example embodiments, the disclosed technology involves the formal verification of a register-transfer-level ('RTL') circuit description produced from a high level synthesis tool (e.g., a C++ or SystemC synthesis tool) relative to the original high level code from which the RTL description was synthesized (e.g., the original C++ or SystemC description) using sub-functional-call-level transactions.

Formal verification using microtransactions

Growing community of inventors

Noida, India

Maheshinder Goyal