Intel Corporation

Mahesh U Wagh

Debendra Das Sharma

David J Harriman

Jasmin Ajanovic

Robert G Blankenship

Sridhar Muthrasanallur

Mark B Rosenbluth

Scott Dion Rodgers

Anil Vasudevan

Prashant Sethi

Ilan Pardo

Ajay V Bhatt

James E Akiyama

Eran Tamari

Doron Shamia

Peter J Barry

Eliezer Weissmann

Ohad Falik

Zuoguo Wu

Arvind Mandhani

Ken Shoemaker

Madhu S Athreya

Woojong Han

Venkatraman Iyer

Shreekant S Thakkar

Su Wei Lim

Abraham Mendelson

Gerald S Pasdast

Michelle C Jen

Robert E Gough

Avi Mendelson

Ting Lok Song

Akshay G Pethe

Joon Teik Hor

Stephen R Van Doren

Swadesh Choudhary

Jeff C Morriss

Mark S Myers

Sridharan Ranganathan

Mohiuddin M Mazumder

Ticky Thakkar

James E Jaussi

Robert J Safranek

Abhishek Singhal

Bruce A Tennant

Narasimha R Lanka

Ananthan Ayyasamy

Prahladachar Jayaprakash Bharadwaj

Avi (Abraham) Mendelson

Wilfred W Kwok

Manjari Kulkarni

Ravishankar Iyer

Lily Pao Looi

David M Lee

Abdul Rahman Ismail

Daniel S Froelich

Michael J Espig

Dimitrios Ziakas

Bassam N Coury

Zhen Fang

Ramacharan Sundararaman

Todd A Hinck

Don Soltis

Lip Khoon Teh

Abdul Hawk Ismail

Xiaobei Li

Mahesh S Natu

Ishwar Agarwal

Bahaa Fahim

Rahul R Shah

Mark S Birrittella

William R Halleck

Lakshmipriya Seshan

Sean O Stalley

Narasimha Lanka

Nitish Paliwal

Peeyush Purohit

Manjula Peddireddy

Prashanth Kalluraya

Azydee Hamid

Anoop Kumar Upadhyay

Ohad Fallk

Ellezer Weissmann

Avi (Arraham) Mendelson

Xiaobel Li

Zuoguo J Wu

Akshay Pethe

In one embodiment, an apparatus includes: a transaction layer circuit to output transaction layer information; and a link layer circuit coupled to the transaction layer circuit, the link layer circuit to receive and process the transaction layer information and to output link layer information to a physical circuit. The link layer circuit may include a first selection circuit to receive and direct cache memory protocol traffic to a selected one of a first logical port and a second logical port. Other embodiments are described and claimed.

System, apparatus and method for handling multi-protocol traffic in data link layer circuitry

An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.

Extending multichip package link off package

In one embodiment, an apparatus includes: a first link layer circuit to perform link layer functionality for a first communication protocol; and a logical physical (logPHY) circuit coupled to the first link layer circuit via a logical PHY interface (LPIF) link, the logPHY circuit to communicate with the first link layer circuit in a flit mode in which the first information is communicated in a fixed width size and to communicate with another link layer circuit in a non-flit mode. Other embodiments are described and claimed.

Logical physical layer interface specification support for PCie 6.0, cxl 3.0, and UPI 3.0 protocols

In one embodiment, an apparatus includes an arbitration circuit with virtual link state machines to virtualize link states associated with multiple communication protocol stacks. The apparatus further includes a physical circuit coupled to the arbitration circuit and to interface with a physical link, where the physical circuit, in response to a retraining of the physical link, is to cause a plurality of the virtual link state machines to synchronize with corresponding virtual link state machines associated with a second side of the physical link, and where at least one of the communication protocol stacks is to remain in a low power state during the retraining and the synchronization. Other embodiments are described and claimed.

System, apparatus and method for synchronizing multiple virtual link states over a package interconnect

An adapter is provided that includes a first interface to couple to a particular device, where link layer data is to be communicated over the first interface, and a second interface to couple to a physical layer (PHY) device. The PHY device includes wires to implement a physical layer of a link, and the link couples the adapter to another adapter via the PHY device. The second interface includes a data channel to communicate the link layer data over the physical layer, and a sideband channel to communicate sideband messages between the adapter and the other adapter over the physical layer. The adapter is to implement a logical PHY for the link.

Link layer-PHY interface adapter

First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.

Multichip package link error detection

Systems, methods, and devices can involve a host device that includes a root complex, a link, and an interconnect protocol stack coupled to a bus link. The interconnect protocol stack can include multiplexing logic to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode, or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode to communicate over the link, and physical layer logic to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.

Flex bus protocol negotiation and enabling sequence

Embodiments may be generally direct to apparatuses, systems, method, and techniques to provide multi-interconnect protocol communication. In an embodiment, an apparatus for providing multi-interconnect protocol communication may include a component comprising at least one connector operative to connect the component to at least one off-package device via a standard interconnect protocol, and logic, at least a portion of the logic comprised in hardware, the logic to determine data to be communicated via a multi-interconnect protocol, provide the data to a multi-protocol multiplexer to determine a route for the data, route the data on-package responsive to the multi-protocol multiplexer indicating a multi-interconnect on-package mode, and route the data off-package via the at least one connector responsive to the multi-protocol multiplexer indicating a multi-interconnect off-package mode. Other embodiments are described.

Techniques to support multiple protocols between computer system interconnects

Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.

Virtualized link states of multiple protocol layer package interconnects

Embodiments may be generally direct to apparatuses, systems, method, and techniques to determine a configuration for a plurality of connectors, the configuration to associate a first interconnect protocol with a first subset of the plurality of connectors and a second interconnect protocol with a second subset of the plurality of connectors, the first interconnect protocol and the second interconnect protocol are different interconnect protocols and each comprising one of a serial link protocol, a coherent link protocol, and an accelerator link protocol, cause processing of data for communication via the first subset of the plurality of connectors in accordance with the first interconnect protocol, and cause processing of data for communication via the second subset of the plurality of connector in accordance with the second interconnect protocol.

Techniques to support multiple interconnect protocols for a common set of interconnect connectors

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Tacoma, WA, United States of America

Mahesh U Wagh