Cisco Technology, Inc.

Intel Corporation

Brocade Communications Systems, Inc.

Mahesh Srinivasa Maddury

Amin Firoozshahian

Omid Azizi

Chandan Egbert

Andreas Kleen

Mahesh Madhav

Kenneth J Tomei

Ashok Raj

Stephen R Van Doren

Alexandre Y Solomatnikov

David Hansen

Mihailo M Stojancic

Eric Gouldey

Justina Provine

John Peter Stevenson

Rajesh M Sankaran

Jian S Liu

Dinesh Ganapathy Dutt

Sanjay Sane

Rupin H Vakharwala

Subbarao Arumilli

Pirabhu Raman

Francisco M Matus

Philip Lynn Leichty

Sarang M Dharmapurikar

John Michael Terry

Henk G Neefs

How Tung Lim

Wing Cheung

Vijay Rangarajan

Ray Kloth

Kung Ling Ko

Various systems and methods for computer memory overcommitment management are described herein. A system for computer memory management includes a memory device to store data and a mapping table; and a memory overcommitment circuitry to: receive a signal to move data in a first block from a memory reduction area in the memory device to a non-memory reduction area in the memory device, the memory reduction area to store data using a memory reduction technique, and the non-memory reduction area to store data without any memory reduction techniques; allocate a second block in the non-memory reduction area; copy the data in the first block to the second block; and update the mapping table to revise a pointer to point to the second block, the mapping table used to store pointers to memory device in the memory reduction area and the non-memory reduction area.

Reservation architecture for overcommitted memory

Processing circuitry for computer memory management includes memory reduction circuitry to implement a memory reduction technique; and reference count information collection circuitry to: access a memory region, the memory region subject to the memory reduction technique; obtain an indication of memory reduction of the memory region; calculate metrics based on the indication of memory reduction of cache lines associated with the memory region; and provide the metrics to a system software component for use in memory management mechanisms.

Hardware-assisted paging mechanisms

A processing device includes a core to execute instructions, and memory management circuitry coupled to, memory, the core and an I/O device that supports page faults. The memory management circuitry includes an express invalidations circuitry, and a page translation permission circuitry. The memory management circuitry is to, while the core is executing the instructions, receive a command to pause communication between the I/O device and the memory. In response to receiving the command to pause the communication, modify permissions of page translations by the page translation permission circuitry and transmit an invalidation request, by the express invalidations circuitry to the I/O device, to cause cached page translations in the I/O device to be invalidated.

Pause communication from I/O devices supporting page faults

Various systems and methods for computer memory management are described herein. A system for computer memory management includes a first memory device including a mapping table; a second memory device including a staging area; a third memory device including a dedup data region; and a controller operable to: receive a memory access request, the memory access request including an address and data; write the data to the staging area; and update the mapping table with the address.

Lazy memory deduplication

Various systems and methods for computer memory management are described herein. A system includes a memory controller to: monitor utilization of a memory device, the memory device used with a memory compression technique; determine that the utilization of the memory device violates a threshold; and initiate a system interrupt to provoke a response, responsive to the utilization of the memory device violating the threshold.

Memory pressure notifier

A LPM search engine includes a plurality of exact match (EXM) engines and a moderately sized TCAM. Each EXM engine uses a prefix bitmap scheme that allows the EXM engine to cover multiple consecutive prefix lengths. Thus, instead of covering one prefix length L per EXM engine, the prefix bitmap scheme enables each EXM engine to cover entries having prefix lengths of L, L+1, L+2 and L+3, for example. As a result, fewer EXM engines are potentially underutilized, which effectively reduces quantization loss. Each EXM engine provides a search result with a determined fixed latency when using the prefix bitmap scheme. The results of multiple EXM engines and the moderately sized TCAM are combined to provide a single search result, representative of the longest prefix match. In one embodiment, the LPM search engine supports 32-bit IPv4 (or 128-bit IPv6) search keys, each having associated 15-bit level 3 VPN identification values.

Longest prefix match scheme

In one embodiment, a method includes receiving a packet at an interface at a network device having a plurality of interfaces connected to a plurality of links forming a bundle, performing a Reverse Path Forwarding (RPF) check on the received packet, and forwarding the packet if it passes the RPF check. The RPF check includes a lookup in an RPF table having a plurality of entries for the bundle, each of the entries including the bundle and one of the links in the bundle, and verification that the interface receiving the packet is connected to one of the links in the bundle identified in the lookup. An apparatus is also disclosed.

Reverse path forwarding lookup with link bundles

In one embodiment, a method includes receiving a multi-destination packet at a switch in communication with a plurality of servers through a network device, identifying a port receiving the multi-destination packet at the switch or a forwarding topology for the multi-destination packet, selecting a bit value based on the identified port or forwarding topology, inserting the bit value into a field in a virtual network tag in the multi-destination packet, and forwarding the multi-destination packet with the virtual network tag to the network device. The network device is configured to forward the multi-destination packet to one or more of the servers based on the bit value in the multi-destination packet. An apparatus for forwarding multi-destination packets is also disclosed.

Forwarding multi-destination packets in a network with virtual port channels

A digital circuit apparatus and method for cryptographic data processing includes steps and means for determining a first modulus having up to a first number of binary digits. A large integer is received which has up to a second number of binary digits that is greater than the first number of binary digits. The first modulus and the large integer are sent to a first processor for computing a first residue of the large integer modulo the first modulus. Before the first processor finishes computing the first residue, the first modulus is also sent to a second processor for computing a second residue of two raised to a power of twice the first number of binary digits modulo the first modulus. The first residue and the second residue are used as input to a third processor that computes a cryptographic result based on the large integer.

Digital circuit apparatus and method for accelerating preliminary operations for cryptographic processing

Techniques for implementing a digital signature algorithm in electronic computer hardware include computing the multiplicative inverse of a particular integer modulo a prime modulus by computing a first quantity modulo the prime modulus. The first quantity substantially equals, modulo the prime modulus, the particular integer raised to a power of a second quantity. The second quantity is two less than the prime modulus. The techniques allow an integrated circuit block to compute a modulo multiplicative inverse, such as for signing and verifying digital signatures, using existing blocks of circuitry that consume considerably less area on a chip, and incur fewer developmental costs, than an implementation of an algorithm conventionally used in software.

Method and apparatus for calculating a multiplicative inverse of an element of a prime field

A method and apparatus for cryptographic data processing, includes determining a first modulus having up to a first number of binary digits. A large integer is received which has up to a second number of binary digits that is greater than the first number of binary digits. The first modulus and the large integer are sent to a first processor for computing a first residue of the large integer modulo the first modulus. Before the first processor finishes computing the first residue, the first modulus is also sent to a second processor for computing a second residue of two raised to a power of twice the first number of binary digits modulo the first modulus. The first residue and the second residue are used as input to a third processor that computes a cryptographic result based on the large integer.

Method and apparatus for accelerating preliminary operations for cryptographic processing

A pre-computation and dual-pass modular operation approach to implement encryption protocols efficiently in electronic integrated circuits is disclosed. An encrypted electronic message is received and another electronic message generated based on the encryption protocol. Two passes of Montgomery's method are used for a modular operation that is associated with the encryption protocol along with pre-computation of a constant based on a modulus. The modular operation may be a modular multiplication or a modular exponentiation. Modular arithmetic may be performed using the residue number system (RNS) and two RNS bases with conversions between the two RNS bases. A minimal number of register files are used for the computations along with an array of multiplier circuits and an array of modular reduction circuits. The approach described allows for high throughput for large encryption keys with a relatively small number of logical gates.

Pre-computation and dual-pass modular arithmetic operation approach to implement encryption protocols efficiently in electronic integrated circuits

Residue number system based pre-computation and dual-pass arithmetic modular operation approach to implement encryption protocols efficiently in electronic integrated circuits

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San Jose, CA, United States of America

Mahesh Srinivasa Maddury