Analog Devices International Unlimited Company

Analog Devices Global

Mahesh Madhavan Kumbaranthodiyil

Jeremy Richard Gorbold

Kirubakaran Ramalingam

Michael C W Coln

Colin Charles Price

Christian Steffen Birk

Gerard Mora Puchalt

Hrishikesh Ravi Mathukkarumukku

Ayan Das

High speed, high dynamic range SAR ADC method and architecture. The SAR DAC comparison method can make fewer comparisons with less charge/fewer capacitors. The architecture makes use of a modified top plate switching (TPS) DAC technique and therefore achieves very high-speed operation. The present disclosure proffers a unique SAR ADC method of input and reference capacitor DAC switching. This benefits in higher dynamic range, no external decoupling capacitory requirement, wide common mode range and overall faster operation due to the absence of mini-ADC.

High speed SAR ADC

Algorithm for high speed SAR ADC

Techniques are described that can be used to extract an offset and a gain of a signal chain, which can be used for digital correction of an analog-to-digital converter (ADC) output to help achieve a life time and temperature stable ADC output. For example, using various techniques, a value for a voltage reference VREF and a value for ground (GND) (or other reference voltage) can be converted, which can then be used to determine gain and offset, respectively, of the signal chain.

ADC output drift correction techniques

An IC can include shared reference voltage buffer circuitry having an amplifier circuit. A commonly-routed amplifier shared output voltage node can be shared between at least two digital-to-analog converters (DACs) respectively via at least first and second individually routed traces from the shared output voltage node to respective first and second local reference voltage nodes at the DACs. Respective first and second routing trace resistances can be based on current draw of the corresponding DAC, such as to provide an equal voltage drop across the first and second routing resistances. This can help avoid voltage contention or conflict at the shared output voltage node from forcing/sensing the voltages at the first and second local reference voltage nodes. In a further example, at least one of the first and second individually routed traces can include a binary tree hierarchical routing arrangement of at least some of the DACs.

Forcing and sensing DACs sharing reference voltage

An analog multiplexer may be used for sampling an input voltage that is capable of having a higher voltage level than an upper supply voltage. The analog multiplexer includes a plurality of input switch circuits and a shorting switch circuit. The plurality of input switch circuits include n-type or p-type laterally diffused field effect transistors (NLDFETs or PLDFETs). At least one of the input switch circuits includes a level shifting switch circuit that is able to sample an input voltage that is greater than the upper supply voltage for the multiplexer. A shorting switch circuit, at an output of the multiplexer, includes a capacitively coupled gate drive circuit and is configured to short a first differential output to a second differential output after the input voltage is sampled.

Analog multiplexer

Methods and apparatus to reduce localized transistor operating temperature increases in fully integrated voltage regulator circuits are provided. Transistor self-heating effects are reduced by dispersing heat more evenly over the integrated circuit die, via use of nested voltage regulator circuits and/or use of more than one transistor in a voltage regulator circuit pass device. An electrically parallel-connected group of multiple individual integrated transistors may be laid out across cooler areas of the integrated circuit die, such as in substantially linear sets or rings of devices near the outer die perimeter. Each transistor in the group may better disperse its own heat if it is thermally segregated from other self-heating devices, as through a minimum physical layout spacing. Transistor bias voltage mismatch tolerances, load currents, and routing resistances may interrelatedly determine the number of individual transistors needed in a group.

Growing community of inventors

Kerala, India

Mahesh Madhavan Kumbaranthodiyil