Uniquify, Incorporated

Uniquify IP Company, LLC

Mahesh Gopalan

Venkat Iyer

David Wu

Jung Gu Lee

A computer-implemented method includes an act of configuring hardware to cause at least a part of the hardware to operate as a double data rate (DDR) memory controller, and to produce a capture clock to time a read data path, where a timing of the capture clock is based on a first clock signal of a first clock, delay the first clock signal to produce a delayed first clock signal, adjust the delay such that at least one clock edge of the delayed first clock signal is placed nearer to at least one clock edge of at least one data strobe (DQS), or at least one signal dependent on a DQS timing, and produce a modified timing of the capture clock based on the delay of the first clock signal.

Double data rate (DDR) memory controller apparatus and method

In accordance with one embodiment, a computer-implemented method is provided, comprising the act of: configuring code or hardware to cause at least part of the hardware to operate as a double data rate (DDR) memory controller and to: produce a capture clock to time a read data path, where a timing of the capture clock is based on a first clock signal of a first clock, delay the first clock signal to produce a delayed first clock signal, adjust the delay such that at least one clock edge of the delayed first clock signal is placed nearer to at least one clock edge of: at least one data strobe (DQS), or at least one signal dependent on a DQS timing, and produce a modified timing of the capture clock based on the delay of the first clock signal.

In accordance with one embodiment, a computer-implemented method is provided, comprising: configuring code to cause at least part of hardware to operate as a double data rate (DDR) memory controller and to produce one or more capture clocks, where: a timing of at least one of the one or more capture clocks is based on a first clock signal of a first clock, the first clock signal is a core clock signal or a signal derived from at least the core clock signal, the at least one of the one or more capture clocks is used to time a read data path, the at least one of the one or more capture clocks is used to capture read data into a clock domain related to a second clock, the first clock and the second clock being related in timing such that at least one of: the second clock is derived from the first clock, or the first clock is derived from the second clock; and providing access to the code.

In accordance with one embodiment, an apparatus is provided, comprising: a double data rate (DDR) memory controller that, when in operation, causes the apparatus to: capture a data bit input signal in a first core domain register that is communicatively coupled to a second core domain register; clock the first core domain register utilizing a first clock; clock the second core domain register utilizing a second clock; maintain a difference in time between an active edge of the second clock and a next active edge of the first clock, such that the difference in time corresponds to a capture clock delay value; and set the capture clock delay value during a power-on initialization calibration operation.

In accordance with one embodiment, an apparatus is provided, comprising: a double data rate (DDR) memory controller that, when in operation, causes the apparatus to: generate a core clock; generate a capture clock; receive a data (DQ) signal that is driven by a DDR memory, or a signal derived from the DQ signal; clock a first core domain register, based, at least in part, on the capture clock; clock a second core domain register, based, at least in part, on the core clock; and set a delay of a core clock delay element, utilizing at least one of: the first core domain register, a signal derived from the first core domain register, the second core domain register, or a signal derived from the second core domain register; wherein the double data rate (DDR) memory controller is configured such that the delay of the core clock delay element is set during a power-on initialization calibration operation.

A method for calibrating capturing read data in a read data path for a DDR memory interface circuit is described. In one version, the method includes the steps of delaying a core clock signal by a capture clock delay value to produce a capture clock signal and determining the capture clock delay value. The capture clock signal is a delayed version of the core clock signal. The timing for the read data path with respect to data propagation is responsive to at least the capture clock signal. In another version, timing for data capture is responsive to a read data strobe or a signal derived therefrom, and a core clock signal or a signal derived therefrom.

Method for calibrating capturing read data in a read data path for a DDR memory interface circuit

Circuits and methods are described for a DDR memory controller where two different DQS gating modes are utilized. These gating modes together ensure that the DQS signal, driven by a DDR memory to the memory controller, is only available when read data is valid. Two types of gating logic are used: Initial DQS gating logic, and Functional DQS gating logic. The Initial gating logic has additional timing margin in the Initial DQS gating value to allow for the unknown round trip timing during initial bit levelling calibration. DQS functional gating is then optimized during further calibration to gate DQS precisely as latency and phase calibration are performed, resulting in a precise gating value for Functional DQS gating. Providing dual gating modes is especially useful when data capture is performed at half the DQS frequency in view of rising clock rates for DDR memories.

Multiple gating modes and half-frequency dynamic calibration for DDR memory controllers

A circuit and method for implementing an adaptive bit-leveling function in an integrated circuit interface is disclosed. During a calibration operation, a pre-loaded data bit pattern is continuously sent from a sending device and is continuously read from an external bus by a receiving device. A programmable delay line both advances and delays each individual data bit relative to a sampling point in time, and delay counts relative to a reference point in time are recorded for different sampled data bit values, enabling a delay to be determined that best samples a data bit at its midpoint. During the advancing and delaying of a data bit, jitter on the data bit signal may cause an ambiguity in the determination of the midpoint, and solutions are disclosed for detecting jitter and for resolving a midpoint for sampling a data bit even in the presence of the jitter.

Circuit for dynamically adaptive bit-leveling by incremental sampling, jitter detection, and exception handling

A circuit and method for implementing a adaptive bit-leveling function in an integrated circuit interface is disclosed. During a calibration operation, a pre-loaded data bit pattern is continuously sent from a sending device and is continuously read from an external bus by a receiving device. A programmable delay line both advances and delays each individual data bit relative to a sampling point in time, and delay counts relative to a reference point in time are recorded for different sampled data bit values, enabling a delay to be determined that best samples a data bit at its midpoint. During the advancing and delaying of a data bit, jitter on the data bit signal may cause an ambiguity in the determination of the midpoint, and solutions are disclosed for detecting jitter and for resolving a midpoint for sampling a data bit even in the presence of the jitter.

Methods for dynamically adaptive bit-leveling by incremental sampling, jitter detection, and exception handling

A DDR memory controller is described wherein a core domain capture clock is created by programmably delaying the core clock of the memory controller. The delay of this capture clock is calibrated during a power on the initialization sequence in concert with a DDR memory in a system environment, thereby minimizing the effects of system delays and increasing both device and system yield. An additional embodiment also includes programmably delaying the incoming dqs signal.

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Milpitas, CA, United States of America

Mahesh Gopalan