Globalfoundries Singapore Pte. Ltd.

Globalfoundries Inc.

Mahesh Bhatkar

Juan Boon Tan

Wanbing Yi

Curtis Chun-I Hsieh

Luke G England

Yi Jiang

Bharat Bhushan

Shunqiang Gong

Neha Nayyar

Shijie Wang

Daxiang Wang

Chin Chuan Neo

Wenjun Liu

Danny Pak-Chum Shum

Fan Zhang

Soh Yun Siah

Yeow Kheng Lim

Lulu Peng

Wei Shao

Hui Liu

Bhushan Bharat

Methods of fabricating a flexible dummy fill to increase MTJ density are provided. Embodiments include forming a first oxide layer; forming lower interconnect layers in the first oxide layer; forming a nitride layer over the first oxide layer and the lower interconnect layers; forming a second oxide layer over the nitride layer; forming bottom electrodes through the second oxide layer and the nitride layer contacting a portion of an upper surface of the lower interconnect layers; forming MTJ structures over the bottom electrodes; forming top electrodes over the MTJ structures; and forming upper interconnect layers over one or more of the top electrodes.

Two pass MRAM dummy solution

Devices and methods for forming a device are disclosed. The method includes providing a substrate having first and second surfaces. At least one through silicon via (TSV) opening is formed in the substrate. The TSV opening extends through the first and second surfaces of the substrate. An alignment trench corresponding to an alignment mark is formed in the substrate. The alignment trench extends from the first surface of the substrate to a depth shallower than a depth of the TSV opening. A dielectric liner layer is provided over the substrate. The dielectric liner layer at least lines sidewalls of the TSV opening. A conductive layer is provided over the substrate. The conductive layer fills at least the TSV opening to form TSV contact. A redistribution layer (RDL) is formed over the substrate. The RDL layer is patterned using a reticle to form at least one opening which corresponds to a TSV contact pad. The reticle is aligned using the alignment mark in the substrate.

Device without zero mark layer

Method of forming embedded MRAM in interconnects using a metal hard mask process and the resulting device are provided. Embodiments include forming a first interlayer dielectric (ILD) layer including a first metal (Mx) level; forming a capping layer over the first ILD layer; forming magnetic tunnel junction (MTJ) structures formed in a second ILD over the first capping layer; forming a second metal (Mx+1) level in the second ILD layer; forming a second capping layer over the second ILD layer; and forming a third metal (Mx+2) level in a third ILD layer over the second capping layer.

Embedded MRAM in interconnects and method for producing the same

A method for forming a MRAM device free of seal ring peeling defect, and the resulting device, are provided. Embodiments include forming magnetic tunnel junction (MTJ) over a metallization layer in a seal ring region of an MRAM device; forming a metal filled via connecting the MTJ and the metallization layer; forming a tunnel junction via over the MTJ; and forming a top electrode over the tunnel junction via.

MRAM device with improved seal ring and method for producing the same

Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a capacitor, where the capacitor includes a first capacitor plate and a second capacitor plate. The first capacitor plate includes a first memory cell, and the second capacitor plate includes a second memory cell. The capacitor is utilized as a functional capacitor in the integrated circuit.

Integrated circuits with vertical capacitors and methods for producing the same

A seal ring structure is disclosed for integrated circuit (IC) packaging. The seal ring includes an inner moisture barrier ring and an outer crack stop ring. Line structures of both the inner and outer rings include chamfered corners. The chamfers of a chamfered corner are devoid of acute angles. No metal line structure for the inner ring is provided at the pad level. The seal ring as described improves the reliability and strength of the structure and hence the seal ring can sustain high stress at the corners of the die during dicing.

Robust chamfer design for seal ring

Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, a method for producing an integrated circuit includes forming a memory cell with a memory cell upper surface. A capping layer is formed overlying the memory cell, and a portion of the capping layer is removed to expose the memory cell upper surface. A memory cell etch stop is formed overlying the memory cell upper surface after the portion of the capping layer is removed to expose the memory cell upper surface. The memory cell etch stop is removed from overlying the memory cell upper surface, and an interconnect is formed in electrical communication with the memory cell.

Integrated circuits with magnetic tunnel junction memory cells and methods for producing the same

A method for fabricating an integrated circuit includes forming a first opening in an upper dielectric layer, the first opening having a first width, forming a second opening in a lower dielectric layer, the lower dielectric layer being below the upper dielectric layer, the second opening having a second width that is narrower than the first width, the second opening being substantially centered underneath the first opening so as to form a stepped via structure, conformally depositing an aluminum material layer in the stepped via structure and over the upper dielectric layer, and forming a passivation layer over the aluminum material layer.

Integrated circuits with aluminum via structures and methods for fabricating the same

A semiconductor chip includes an active area including a plurality of integrated circuit structures, a seal ring enclosing the active area, a corner area of the semiconductor chip that is outside of the seal ring, and an electronic test structure disposed within the corner area. Semiconductor wafers including the above-noted semiconductor chips, as well as methods for fabricating semiconductor wafers including the above-noted semiconductor chips, are also disclosed.

Semiconductor chips with seal rings and electronic test structures, semiconductor wafers including the semiconductor chips, and methods for fabricating the same

Magnetic core inductors implemented on integrated circuits and methods for fabricating such magnetic core inductors are disclosed. An exemplary magnetic core inductor includes a bottom magnetic plate that includes a center portion and first, second, third, and fourth extension portions extending from the center portion. The exemplary magnetic core inductor includes an interlayer dielectric layer disposed over the bottom magnetic plate, and within the interlayer dielectric layer, first, second, third, and fourth via trenches extending above a respective one of the first, second, third, and fourth extension portions, and a fifth via trench extending above the center portion. The magnetic core inductor further includes a stacked-ring inductor coil including a plurality of inductor rings surrounding the fifth via trench and a top magnetic plate including a center portion and first, second, third, and fourth extension portions extending from the center portion.

Integrated circuits including magnetic core inductors and methods for fabricating the same

Wafer-level methods of forming circuit elements, such as multilayer inductors or transformers, are provided. The methods include, for instance: forming, in at least one layer above a substrate, at least one conductive portion of the circuit element; providing an uncured polymer-dielectric material surrounding, at least in part, and overlying the conductive portion(s) of the element; partially curing the polymer-dielectric material to obtain a partially-hardened, polymer-dielectric material; and polishing the partially-hardened, polymer-dielectric material down to the conductive portion(s). The polishing planarizes the partially-hardened, polymer-dielectric material and exposes an upper surface of the conductive portion(s) to facilitate forming at least one other conductive portion of the element above and in electrical contact with the conductive portion(s). After polishing, curing of the polymer-dielectric material is completed. In one embodiment, the conductive portion(s) and the other conductive portion(s) define, at least in part, a conductive coil(s) of the element.

Fabrication of multilayer circuit elements

A semiconductor device is disclosed. The semiconductor device includes a substrate comprises a plurality of metal layers. The semiconductor device also includes dielectric posts disposed in the metal layers. The density of the dielectric posts in the metal layers is equal to about 15-25%.

Growing community of inventors

Singapore, Singapore

Mahesh Bhatkar