Qualcomm Incorporated

Mahesh Aia

Dileep Marchya

Sushil Chauhan

Dhaval Kanubhai Patel

Sudeep Ravi Kottilingal

Kalyan Thota

Srinivas Pullakavi

Prashant Nukala

Nagamalleswararao Ganji

Mohammed Naseer Ahmed

The present disclosure relates to methods and devices for display processing including an apparatus, e.g., a DPU, a compositor, a compositor backend, a DPU driver, and/or DPU firmware. In some aspects, the apparatus may receive content information for each of one or more layers of a frame. The apparatus may also determine whether the content information for each of the one or more layers includes at least one priority format. Additionally, the apparatus may determine a priority order of the one or more layers when the content information for at least one of the one or more layers includes at least one priority format. The apparatus may also map each of one or more display overlay resources to each of the one or more layers based on the determined priority order of the one or more layers.

Methods and apparatus for plane planning for overlay composition

This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for parallelization of GPU composition with DPU topology selection. A processor may receive an indication of a plurality of application layers for composition at a first processor (e.g., a DPU) and a second processor (e.g., a GPU). The processor may select one or more first application layers of the plurality of application layers for attempted composition at the first processor and one or more second application layers of the plurality of application layers for composition at the second processor. The processor may transmit each of the one or more first application layers to the first processor for composition and each of the one or more second application layers to the second processor for composition.

Parallelization of GPU composition with DPU topology selection

In some aspects, the present disclosure provides a method for generating a frame. The method includes receiving a first fence indicating that a first frame stored in a display processor unit (DPU) buffer has been consumed by a hardware component. The method also includes in response to receiving the first fence, fetching a plurality of layers from an application buffer, the plurality of layers corresponding to a second frame. The method also includes determining to use both a DPU and a graphics processing unit (GPU) to process the plurality of layers for composition of the second frame. The method also includes fetching the first fence from the DPU buffer and generating a second fence.

Low latency composer

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San Diego, CA, United States of America

Mahesh Aia