Synopsys, Inc.

Altera Corporation

Intel Corporation

Broadcom Corporation

International Business Machines Corporation

Mahesh A Iyer

Amir H Mottaez

Manoj Thawani

Robert L Walker

Ankireddy Nalamalpu

Scott J Weber

Aravind Raghavendra Dasu

Henry S Ptasinski

Manas Deb

Jeff Vadasz

Vasudeva M Kamath

Edward Carter

Ravi Prakash Gutala

Mahesh K Kumashikar

Atul Maheshwari

Saurabh Adya

Archanna Srinivasan

Ashish Kapoor

Dheeraj R Subbareddy

Love Singhal

Eriko Nurvitadhi

Md Altaf Hossain

Dana How

Carl Ebeling

Sudipto Kundu

Yuet Li

David Wolk Mendel

Sean R Atsatt

Raymond Hayes

Yi Peng

David Lawrence Cohen

Dhananjay Raghavan

Martin Langhammer

Herman Henry Schmit

Kapil Chhabra

Jawad Basit Khan

Richard L Coulson

Ning Cheng

Albert Fazio

Ilya K Ganusov

James Loran Ball

Patrick Koeberl

Suresh Srinivasan

Pei-Hsin Ho

Jing Chyuarn Lin

Leon Stok

Anand Arunachalam

Andrew James Sullivan

Prashant Saxena

Kevin Michael Harer

Narendra V Shenoy

Vishal Khandelwal

Yury Gonikberg

Kalen Brunham

Matthew I Adiletta

Robert F Damiano

Jesmin Jahan Tithi

Vadali Mahadev

Kermin E ChoFleming, Jr

Changge Qiao

Nikolay Rubanov

Hi-Keung Tony Ma

Vikram Saxena

Xiangyong Wang

Brandon Gordon

Rajiv Mongia

Ian Kuon

Krishna Nagar

Terence Magee

Scott Whitty

Ted Edward Carter

Henry S Ptasinki

Clinton W Brown

Rajnish K Prasad

Shounak Dhar

Systems or methods of the present disclosure may provide for gradually adjusting a frequency of a clock signal. When transitioning from a configuration mode to a user mode, a clock of an integrated circuit (e.g., a field-programmable gate array or FPGA) may quickly (e.g., instantaneously) switch from a low configuration mode frequency to a high user mode frequency. This rapid increase in clock frequency may cause an inrush current and corresponding current-resistance voltage (IR) drop. To reduce or avoid the inrush current and IR drop, a frequency of the clock may be gradually ramped up from the configuration mode frequency to the user mode frequency.

Controlled transition between configuration mode and user mode to reduce current-resistance voltage drop

Systems and methods are provided for generating a circuit design for an integrated circuit using a circuit design tool. The circuit design tool determines maximum junction temperatures for circuit blocks in the circuit design for the integrated circuit. The circuit design tool determines defects values for the circuit blocks using the maximum junction temperatures for the circuit blocks. The circuit design tool determines a defects value for the circuit design based on the defects values for the circuit blocks. The circuit design tool determines a maximum junction temperature for the circuit design based on a comparison between the defects value for the circuit design and a target defects value for the circuit design. The circuit design tool can dynamically reconfigure configurable logic circuit blocks to improve the power, the performance, and the thermal profile to achieve an optimal junction temperature per circuit block.

Systems and methods for circuit design dependent programmable maximum junction temperatures

An integrated circuit includes a monitored circuit and a signal analyzer circuit. The signal analyzer circuit includes a logic circuit that determines if a condition signal satisfies a condition to generate an output signal. A first-in-first-out (FIFO) buffer circuit stores opportunistic data indicated by a monitored signal received from the monitored circuit in response to the output signal indicating if the condition signal satisfies the condition. A communication channel transmits the opportunistic data stored in the FIFO buffer circuit outside the integrated circuit.

Circuits and methods for accessing signals in integrated circuits

Systems or methods of the present disclosure may provide efficient power consumption for programmable logic devices based on reducing guardband voltages. A programmable logic device may include circuit monitors to mimic critical paths of an implemented circuit design and generate timing information based on the critical paths. A controller on the programmable logic device may adjust the voltage guardband based on the timing information.

Systems and methods to reduce voltage guardband

Systems or methods of the present disclosure may provide for operating a programmable fabric including multiple programmable elements organized into a number of power domains that utilize a common voltage within the respective power domains. A current sensor senses a current of the programmable fabric. When the sensed current has crossed a threshold, the programmable fabric changes the number of power domains.

Switch based on load current

Systems or methods of the present disclosure may provide efficient electric power consumption of programmable logic devices based on providing different voltage levels to different portions (e.g., voltage islands) of the programmable logic device. For example, the programmable logic device may include circuitry to provide different voltage levels to different voltage islands. The programmable logic device may implement and operate logic configurations with different operating parameters using different operating voltages for efficient electric power consumption.

Power management using voltage islands on programmable logic devices

A circuit system includes a power control circuit that generates multiple voltage identifiers. Multiple voltage regulator circuits generate multiple supply voltages based on the voltage identifiers. The supply voltages are provided to multiple integrated circuit dies. The power control circuit varies the voltage identifiers based on changes in metrics associated with the integrated circuit dies to cause the voltage regulator circuits to vary the supply voltages. Integrated circuit dies receive supply voltages from voltage regulator circuits through power delivery networks. The integrated circuit dies provide voltage sense signals that indicates the supply voltages. The voltage regulator circuits adjust the supply voltages based on the voltage sense signals to compensate for voltage drops in the power delivery networks.

Supply voltage control systems and methods for integrated circuits

Embodiments of the present disclosure are related to dynamically adjusting a timing and/or power model for a programmable logic device. In particular, the present disclosure is directed to adjusting a timing and/or power model of the programmable logic device that operates at a voltage level that is not other than a predefined voltage defined by a voltage library. A system of the present disclosure may interpolate between voltage levels defined by the voltage libraries to generate a new voltage library for the programmable logic device. A timing and/or power model may be generated for the programmable logic device based on the new voltage library and the programmable logic device may be analyzed using the timing and/or power model at the interpolated voltage. The timing and/or power model may be used to generate a bitstream that is used to program the integrated circuit.

Dynamically scalable timing and power models for programmable logic devices

A circuit system includes a first integrated circuit die having a first group of circuits configured to perform a first set of operations. The circuit system also includes a second integrated circuit die having a second group of circuits configured to start performing a second set of operations with a delay after the first group of circuits starts performing the first set of operations to reduce power supply voltage droop. The operations performed by the first and second groups of circuits can be interleaved with a fixed or a variable delay. Logic circuits can be partitioned into the first and the second groups of circuits based on predicted switching activity of the logic circuits. Decoupling capacitors in integrated circuit dies can be coupled together to reduce droop in a supply voltage during a high current event.

Circuit systems and methods for reducing power supply voltage droop

A circuit system includes a first voltage regulator circuit that generates a first supply voltage for an integrated circuit die based on a first control signal. The first voltage regulator circuit generates a first feedback signal based on the first supply voltage. The circuit system also includes a second voltage regulator circuit that generates a second supply voltage for an integrated circuit die based on a second control signal. The second voltage regulator circuit generates a second feedback signal based on the second supply voltage. The circuit system also includes a third voltage regulator circuit that generates the first control signal based on the first feedback signal and the second control signal based on the second feedback signal. The circuit system may include fully integrated, on-board, and on-package voltage regulator circuits.

Voltage regulator circuit systems and methods

A method includes mapping an aging measurement circuit (AMC) into the core fabric of an FPGA and operating the AMC for a select time period. During the select period of time, the AMC counts transition of a signal propagating through the AMC. Timing information based on the counted transitions is stored in a timing model in a memory. The timing information represents an aging characteristic of the core fabric at a time that the AMC is operated. An EDA toolchain uses the timing information in the timing model to generate a timing guard-band for the configurable IC die. The AMC is removed from the core fabric and another circuit device is mapped and fitted into the core fabric using the generated timing guard-band models. The circuit device is operated in the configurable IC die based on the timing guard-band models.

On-die aging measurements for dynamic timing modeling

An integrated circuit device may include a programmable fabric die having programmable logic fabric and configuration memory that may configure the programmable logic fabric. The integrated circuit device may also include a base die that may provide fabric support circuitry, including memory and/or communication interfaces as well as compute elements that may also be application-specific. The memory in the base die may be directly accessed by the programmable fabric die using a low-latency, high capacity, and high bandwidth interface.

Fast memory for programmable devices

A three dimensional circuit system includes a first integrated circuit die having a core logic region that has first memory circuits and logic circuits. The three dimensional circuit system includes a second integrated circuit die that has second memory circuits. The first and second integrated circuit dies are coupled together in a vertically stacked configuration. The three dimensional circuit system includes third memory circuits coupled to the first integrated circuit die. The third memory circuits reside in a plane of the first integrated circuit die. The logic circuits are coupled to access the first, second, and third memory circuits and data can move between the first, second, and third memories. The third memory circuits have a larger memory capacity and a smaller memory access bandwidth than the second memory circuits. The second memory circuits have a larger memory capacity and a smaller memory access bandwidth than the first memory circuits.

Three dimensional circuit systems and methods having memory hierarchies

An integrated circuit die includes a core fabric configurable to include an aging measurement circuit and a device manager coupled to the core fabric to operate the aging measurement circuit for a select period of time. The aging measurement circuit includes a counter to count transitions of a signal propagating through the aging measurement circuit during the select period of time when the aging measurement circuit is operating. The transitions of the signal counted by the counter during the select period of time are a measure of an aging characteristic of the integrated circuit die.

Systems and methods are provided for using an integrated circuit design tool to analyze timing requirements of a circuit design for an integrated circuit. A slack is calculated for a timing path in the circuit design that fails to satisfy a timing constraint. The slack is decomposed into multiple categories of delays in the timing path. The categories of delays for the slack may include intrinsic margin, clock skew, logic delay, and fabric interconnect delay. The logic delay may include local interconnect delay and logic circuit delay. The fabric interconnect delay may include delays in interconnect elements that are used to make connections between larger blocks of the logic circuits. Different optimization strategies are provided to solve the timing constraint failure for each of the different categories of slack breakdown. Slack profiles of the entire design in each of the four categories of slack are also provided.

Techniques for providing optimizations based on categories of slack in timing paths

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Fremont, CA, United States of America

Mahesh A Iyer