Ciena Corporation

Mahdi Parvizi

Naim Ben-Hamida

Sadok Aouini

Yuriy Greshishchev

Douglas Stuart McPherson

Ahmad Abdo

Timothy James Creasy

Lukas Jakober

Calvin Plett

Tingjun Wen

Matthew Mikkelsen

Robert G Gibbins

Jacob Pike

Anna Sakharova

Gordon W Roberts

David V Plant

Khaled Maamoun

Bilal Riaz

Ahmed Emara

Nicolás Abadía Calvo

Luhua Xu

David Patel

Lukas Jakpber

Douglas Mcpherson

Sadok Aouinin

A circuit includes a programmable frequency divider which receives a high-speed clock, f, as an input and which provides a modulated reference clock as an output; a Sigma-Delta modulator which receives a Frequency Control Word (FCW) and which is connected to the programmable frequency divider to receive the modulated reference clock as a sample clock and to control an average frequency of the modulated reference clock; and an integer-N Phase Lock Loop (PLL) which receives the modulated reference clock and outputs a clock output.

Fractional frequency synthesis by sigma-delta modulating frequency of a reference clock

Systems and methods for controlling network configurations or assignments are provided. A method, according to one implementation, includes a step of calculating transmission characteristics between each pair of a plurality of pairs of modems at opposite ends of a Dense Wavelength-Division Multiplexing (DWDM) transport link using specifications of the modems measured during production. The method also includes the step of selecting a pair of modems from the plurality of pairs of modems based on results obtained by calculating the transmission characteristics and based on one or more user-defined service requests.

Matching transmitters with receivers for making network-level assignments

Described are apparatus and methods for low power frequency clock generation and distribution. A device includes a low power generation and distribution circuit configured to generate and distribute a differential 1/N sampling frequency (F)(F/N) clock, wherein N is larger or equal to 2, and a differential frequency doubler configured to generate a single-ended multiplied frequency clock from the differential F/N frequency clock, and convert the single-ended multiplied frequency clock to a differential multiplied frequency clock for use by one or more data processing channels.

Apparatus and methods for low power frequency clock generation and distribution

Clock circuits, components, systems and signal processing methods enabling digital communication are described. A phase locked loop device derives an output signal locked to a first reference clock signal in a feedback loop. A common phase detector is employed to obtain phase differences between a copy of the output signal and a second reference clock signal. The phase differences are employed in an integral phase control loop within the feedback loop to lock the phase locked loop device to the center frequency of the second reference signal. The phase differences are also employed in a proportional phase control loop within the feedback loop to reduce the effect of imperfect component operation. Cascading the integral and proportional phase control within the feedback loop enables an amount of phase error to be filtered out from the output signal.

High-order phase tracking loop with segmented proportional and integral controls

Described are apparatus and methods for high frequency clock generation. A circuit includes a phase frequency detector (PFD) which outputs differential error clocks based on comparison of differential reference clocks and differential feedback clocks, which are at a first frequency. A controlled oscillator (CO) connected to the PFD, which adjusts a frequency of the CO based on the differential error clocks to generate differential clocks at a second frequency, which is a multiple of the first frequency. A quadrature clock generator connected to the CO, which generates differential quadrature clocks at the second frequency from the differential clocks, where the differential feedback clocks are generated from the differential clocks and one pair of the differential quadrature clocks. A frequency doubler which doubles each pair of the differential quadrature clocks and outputs fully differential and balanced clocks at a third frequency for distribution, which is a multiple of the second frequency.

Apparatus and methods for high frequency clock generation

Described is a digital fractional phase locked loop (DFPLL) with a current mode low pass filter. The DFPLL includes a binary phase frequency detector (BPFD) configured to output a directional pulse based on comparison of a reference clock and a feedback clock, a current mode low pass filter connected to the BPFD, and a current controlled oscillator (CCO) connected to the current mode low pass filter. The current mode low pass filter configured to output a control current based on at least the directional pulse when a current steering switch directly controlled by the directional pulse switches to the CCO. The CCO configured to adjust a frequency of the CCO based on the control current to generate an output clock. The feedback clock based on the output clock and the reference clock aligned with the feedback clock by adjusting the frequency of the output clock until frequency and phase lock.

Apparatus and methods for digital fractional phase locked loop with a current mode low pass filter

Described are apparatus and methods for low power clock generation in multi-channel high speed devices. In implementations, a multi-channel data processing device includes a low frequency clock generation and distribution circuit configured to generate and distribute a 1/N sampling frequency (F)(F/N) clock, wherein N is larger or equal to 8, and multiple data processing channels connected to the low frequency generation and distribution circuit. Each data processing channel including input ports associated with different operating frequency clocks, and a channel local clock generation circuit comprising multipliers associated with some of the input ports, each multiplier configured to multiply the F/N frequency clock to locally generate an operating frequency clock associated with an input port of the input ports.

Apparatus and methods for low power clock generation in multi-channel high speed devices

Described herein is a digital phase locked loop (PLL) which includes a phase frequency detector (PFD) outputting a pulse width modulated (PWM) up pulse and a PWM down pulse based on comparison of a reference clock and a feedback clock, a digital integral circuit connected to the PFD, the digital integral circuit outputting a digital control signal based on the PWM up and down pulses, and a controlled oscillator (CO) connected to the digital integral circuit and an output and input of the PFD. The CO receiving the PWM up and down pulses from the PFD and adjusting a frequency of the CO based on the digital control signal and the PWM up and down pulses to generate an output clock. The feedback clock is based on the output clock and the reference clock is aligned with the feedback clock by adjusting the output clock frequency until frequency/phase lock.

Apparatus and methods for digital phase locked loop with analog proportional control function

Described herein are apparatus and methods for realization of time interleaved digital-to-analog converters (DACs) by detecting and aligning phase mismatches. In an implementation, a N-time interleaved DAC includes N DACs and N replica DACs, where a first set of N/2 DACs operate at a clock A and a second set of N/2 DACs operate at a clock B, and where N is at least two. The phase detector generates a phase detection output by comparing outputs of the first and second set of N/2 replica DACs with a multiplexor (MUX) clock, where the MUX clock is a multiple of a frequency of the clock A or the clock B. The clock A and the clock B are aligned with the MUX clock by advancing a phase of the clock A and the clock B until the phase detection output achieves a zero crossing.

Apparatus and methods for realization of N time interleaved digital-to-analog converters

Disclosed herein are architectures for low power, low voltage traveling wave Mach-Zehnder optical modulators. By combining single-ended series push-pull modulator configurations with differential dual-drive modulator configurations, the advantages of each type may be utilized. In particular, the halved capacitance of single-ended series push-pull modulators may reduce microwave losses, thereby improving bandwidth performance within modulator configurations. Moreover, reduced required drive voltage of dual-drive modulators coupled with increased impedance may advantageously minimize the power consumption and maximize efficiency in the differential traveling wave series push-pull Mach-Zehnder modulator configurations disclosed herein.

Fully differential traveling wave series push-pull mach-zehnder modulator

Digital jitter accumulation reduction techniques and circuits are proposed to mitigate jitter accumulation in Voltage Controlled Oscillators (VCOs). In order to reduce jitter accumulation, employing a pair of identical injection locked VCOs is proposed in an interleaved fashion. Further jitter accumulation reductions can be provided by employing a plurality of identical injection locked VCOs selected in a cascading fashion. Yet further jitter accumulation reductions can be provided by resetting the deselected VCO(s).

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Kanata, Canada

Mahdi Parvizi