University of Minnesota

Micron Technology Incorporated

Mahdi Jamali

Jian-Ping Wang

Yasuko Hattori

Daniele Vimercati

Xinwei Guo

William A Melton

Yang Lv

Zhengyang Zhao

Mahendra Dc

Angeline Klemm Smith

Yanfeng Jiang

Hyung-il Kim

Sachin S Sapatnekar

Zhaoxin Liang

Andre Mkhoyan

Danielle Hickey

Meghna G Mankalale

A memory device may include a digit line, a ferroelectric memory cell coupled with the digit line, a first capacitor including a first node and a second node, the first node coupled with the digit line using a first path and the second node coupled with the digit line using a second path different from the first path, and a switching component positioned in the second path and coupled with the second node of the first capacitor and the digit line, the switching component configured to selectively couple the second node of the first capacitor with the digit line. In some cases, the memory device may further include a second capacitor coupled with the digit line and the second node of the first capacitor.

Techniques and devices for canceling memory cell variations

Methods, systems, and devices for self-referencing sensing schemes with coupling capacitance are described. A sense component of a memory device may include a capacitive coupling between two nodes of the sense component. The capacitive coupling may, in some examples, be provided by a capacitive element of the sense component or an intrinsic capacitance between features of the sense component. An example of a method employing such a sense component for detecting a logic state stored by a memory cell may include generating a first sense signal at one of the nodes while the node is coupled with the memory cell, and generating a second sense signal at the other of the nodes while the other node is coupled with the memory cell. The sense signals may be based at least in part on the capacitive coupling between the two nodes.

Self-referencing sensing schemes with coupling capacitance

A material may include at least one of BiSe, BiTe, or SbTe, where x is greater than 0 and less than 1. In some examples, the material exhibits a Spin Hall Angle of greater than 3.5 at room temperature. The disclosure also describes examples of devices that include a spin-orbit torque generating layer, in which the spin-orbit torque generating layer includes at least one of BiSe, BiTe, or SbTe, where x is greater than 0 and less than 1. In some examples, the spin-orbit torque generating layer exhibits a Spin Hall Angle of greater than 3.5 at room temperature.

Spin orbit torque generating materials

This disclosure describes an example device that includes a first contact line, a second contact line, a spin-orbital coupling channel, and a magnet. The spin-orbital coupling channel is coupled to, and is positioned between, the first contact line and second contact line. The magnet is coupled to the spin-orbital coupling channel and positioned between the first contact line and the second contact line. A resistance of the magnet and spin-orbital coupling channel is a unidirectional magnetoresistance.

Two-terminal spintronic devices

A memory device may include a digit line, a ferroelectric memory cell coupled with the digit line, a first capacitor including a first node and a second node, the first node coupled with the digit line using a first path and the second node coupled with the digit line using a second path different from the first path, and a switching component positioned in the second path and coupled with the second node of the first capacitor and the digit line. The switching component may selectively couple the second node of the first capacitor with the digit line. In some cases, the memory device may also include a second capacitor coupled with the digit line and the second node of the first capacitor.

Canceling memory cell variations by isolating digit lines

An article may include a substantially perpendicularly magnetized free layer having a first magnetic orientation in the absence of an applied magnetic field. The article may also include a spin Hall channel layer configured to conduct a spin current configured to subject the perpendicularly magnetized free layer to a magnetic switching torque and a substantially in-plane magnetized bias layer configured to bias the substantially perpendicularly magnetized free layer to a second magnetic orientation. The second magnetic orientation is different than the first magnetic orientation and is out of a plane of the substantially perpendicularly magnetized free layer.

Spin hall effect magnetic structures

In some examples, an electronic device comprising an input ferroelectric (FE) capacitor, an output FE capacitor, and a channel positioned beneath the input FE capacitor and positioned beneath the output FE capacitor. In some examples, the channel is configured to carry a magnetic signal from the input FE capacitor to the output FE capacitor to cause a voltage change at the output FE capacitor. In some examples, the electronic device further comprises a transistor-based drive circuit electrically connected to an output node of the output FE capacitor. In some examples, the transistor-based drive circuit is configured to deliver, based on the voltage change at the output FE capacitor, an output signal to an input node of a second device.

Fast magnetoelectric device based on current-driven domain wall propagation

A device including a spin channel to transport a spin current, a nano-oscillator, and a magnetoresistive device that receives the spin current from the nano-oscillator. The nano-oscillator includes a magnetization state that oscillates between a first state and a second state in response to an input voltage or current. The oscillation of the nano-oscillator may induce the spin current within the spin channel. The magnetoresistive device includes a magnetization state that is set based at least in part on the received spin current.

Spin current generation with nano-oscillator

A device including a conductive layer configured to output a spin-current based on an analog input value, a plurality of magnetoresistive devices, and an encoder configured to output a digital value. Each of the magnetoresistive devices may be configured to receive a different reference voltage on a first side and the spin-current on a second side. The magnetization state of each of the magnetoresistive devices is set by respective reference voltages and the spin-current. The encoder may include a plurality of digital bits that is a digital representation of the analog input value based on the magnetization states of the magnetoresistive devices.

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Folsom, CA, United States of America

Mahdi Jamali