Globalfoundries Inc.

Globalfoundries U.S. Inc.

Mahbub Rashed

Juhan Kim

Navneet Jain

Jongwook Kye

Suresh Venkatesan

Lei Yuan

Subramani Kengeri

Irene Y Lin

Marc Laurent Tarabbia

Yunfei Deng

Chinh Nguyen

David Doman

Yuansheng Ma

Jeff Kim

Scott C Johnson

Steven R Soss

Andy T Nguyen

Anurag Mittal

Shivraj Gurpadappa Dharne

Vivek Raj

Uttam K Saha

Qi Xiang

Yan E Wang

Jason Eugene Stephens

Hidekazu Yoshida

Rod Augur

Shibly S Ahmed

David C Pritchard

Jia Zeng

Xuelian Zhu

Anil Kumar

James Mazza

Sushama Davar

Sangmoon J Kim

Arif A Siddiqi

Seung-Hyun Rhee

Yuan Lei

Qinglei Wang

Dinesh Somasekhar

Peter Baars

Alain F Loiseau

Harry Jay Levinson

Ali Keshavarzi

Sunil Kumar

Srikanth Balaji Samavedam

George Jonathan Kluth

Roderick Alan Augur

Manjunatha Govinda Prabhu

Nigel Chan

Tuhin Guha Neogi

Norman Chen

Vikrant Kumar Chauhan

Rick J Carter

Sanjay Parihar

Nader Magdy Hindawy

Ingolf Lorenz

Jian Liu

Irene Yuh-Ling Lin

Paul D Mesa

James B Gullette

Scott Johnson

Zahir Yilmaz Alpaslan

Jongwook K E

Xiang Qi

Marc Tarrabia

Steve Soss

Larry Ho

James Benjamin Gullette

Irene Y L Lin

The present disclosure relates to semiconductor structures and, more particularly, to antenna structures and methods of manufacture. The structure includes an antenna cell comprising a single P-well isolated by a deep trench isolation structure and including at least one diffusion region.

Antenna structure

The present disclosure relates to semiconductor structures and, more particularly, to local interconnect power rails merged with upper power rails and methods of manufacture. The structure includes: an active cell including contacts enclosed in active regions; at least one local interconnect power rail connecting to the contacts of the active regions; and at least one power rail above and connected to the at least one local interconnect power rail.

Local interconnect power rails and upper power rails

The present disclosure relates to semiconductor structures and, more particularly, to cell layouts in semiconductor structures and methods of manufacture. A structure includes: a plurality of abutting cells each of which include transistors with gate structures having diffusion regions; a contact spanning across abutting cells of the plurality of abutting cells and contacting to the diffusion regions of separate cells of the abutting cells; and a continuous active region spanning across the plurality of abutting cells, wherein the continuous active region includes a drain-source abutment with L-shape construct, a source-source abutment with U-shape construct, and a drain-drain abutment with a filler cell located between a drain-drain abutment.

Cell layouts

Disclosed are a pixel and a compact memory-in-pixel display (e.g., implemented in a fully-depleted semiconductor-on-insulator processing technology platform). A block of electronic components for a pixel includes a memory cell array, a driving circuit for an LED, and a logic circuit connected between the memory cell array and driving circuit. The memory cell array is above a Pwell, the driving circuit is above an adjacent Nwell, and the logic circuit includes P-type transistors on the Nwell and N-type transistors on the Pwell. A pixel array is above alternating P and N wells with a single buried Nwell below. Specifically, each column of pixels is above adjacent elongated P and N wells and, within each column, adjacent pixels have mirrored layouts. Furthermore, adjacent columns of pixels are above two elongated wells of one type and a shared elongated well of the opposite type therebetween and the adjacent columns have mirrored layouts.

Compact memory-in-pixel display structure

Disclosed are embodiments of a computer-aided design system and corresponding method for power-optimized timing closure of an integrated circuit (IC) design. In the embodiments, a cell library includes sets of cells, where each cell in the same set has the same internal structure but different combinations of cell boundary isolation structures associated with different passive delay values. Timing closure includes replacement of a cell in a previously generated layout with another cell from the same set in order to adjust delay (e.g., increase delay) of a data signal or clock signal and, thereby facilitate fixing of a previously identified violation of a timing constraint. By eliminating or at least minimizing the need to insert buffer and/or inverter cells into a layout to add delay to a data signal and/or a clock signal during timing closure, the embodiments avoid or at least limit concurrent increases in power consumption and area consumption.

System and method employing power-optimized timing closure

A semiconductor device including four transistors. Gates of first and third transistors extend longitudinally as part of a first linear strip. Gates of second and fourth transistors extend longitudinally as part of a second linear strip parallel to and spaced apart from first linear strip. Aligned first and second gate cut isolations separate gates of first and second transistor from gates of third transistor and fourth transistor respectively. First and second CB layers connect to the gate of first transistor and second transistor respectively. CA layer extends longitudinally between first end and second end of CA layer connects to CB layers. CB layers are electrically connected to gates of first transistor adjacent first end of CA layer and second transistor adjacent second end of CA layer respectively. CA layer extends substantially parallel to first and second linear strips and is substantially perpendicular to first and second CB layers.

Semiconductor device with transistor local interconnects

An apparatus includes a series of pipeline stages that have logic components connected to supply output data to latch components, timing correction blocks connected to the latch components, and a memory component connected to supply a correction pattern to the timing correction blocks. The timing correction blocks have a buffer connected to a multiplexor. The correction pattern controls whether the multiplexor receives an adjusted clock signal through the buffer to control whether the timing correction blocks supply an unadjusted clock signal or the adjusted clock signal to the latch components.

Post-manufacture latch timing control blocks in pipelined processors

Disclosed is a semiconductor structure including a substrate with a first type conductivity (e.g., a P− silicon substrate); a deep well region within the substrate and having a second type conductivity (e.g., a deep Nwell); alternating stripes of first and second well regions (e.g., of Pwells and Nwells with each Pwell positioned laterally between and abutting two Nwells) within the substrate above and traversing the deep well region; and an isolation region (e.g., an Nwell-type isolation region) dividing a first well region (e.g., a Pwell) into sections. Since the sectioned first well region has the first type conductivity and since the isolation region, the deep well region below, and the adjacent well regions on either side have the second type conductivity, the different sections of the sectioned well region are electrically isolated and devices formed on an insulator layer above the different sections can be subjected to different back-biasing conditions.

Semiconductor structure including sectioned well region

A disclosed structure includes a section (e.g., an always on (AON) section) with at least one N-channel transistor (NFET) and at least one P-channel transistor (PFET). The structure further includes a switch with first and second inputs connected to receive positive and negative bias voltages, respectively, and first and second outputs connected to bias back gates of the NFET(s) and PFET(s), respectively, of the section. The structure is also configured to generate select signals for controlling the input-to-output connections established by the switch. In a power saving mode, these signals cause the switch to establish input-to-output connections resulting only in reverse back biasing of the NFET(s) and PFET(s) of the section. In a functional mode, these signals can cause the switch to establish input-to-output connections resulting in either forward back biasing or reverse back biasing. Also disclosed is a method of operating the structure.

Back bias control for always-on circuit section enabling leakage reduction during power saving mode

Integrated structures include (among other components) a deep well structure having a first impurity, well rows contacting the deep well structure and having a second impurity, a well contact ring enclosing the well rows within an enclosed area, a transistor layer on the well rows, transistors within the transistor layer, and at least one ring-enclosed contact contacting the deep well structure. The ring-enclosed contact is positioned within the enclosed area. Such structures further include a well contact connection contacting the well contact ring and the ring-enclosed contact.

Deep nwell contact structures

Embodiments of the disclosure provide a structure and related method to delay data signals through a data path using a lockup latch driven by the inverse of a clock signal. A structure according to the disclosure provides a launch pulse latch coupled to a capture pulse latch through a data path. The data path includes a combinational logic for processing signals within the data path. An edge of a clock signal drives the launch pulse latch and the capture pulse latch. A lockup latch is within the data path between the launch pulse latch and the capture pulse latch. An inverse of the clock signal drives the lockup latch.

Structure and method for delaying of data signal from pulse latch with lockup latch

Embodiments of the disclosure provide a circuit structure and related method to provide a radiation resistant memory cell. A circuit structure may include a first latch having an input node and an output node. A second latch has an input node and an output node, in which the output node of the second latch is coupled to the input node of the first latch, and the input node of the second latch is coupled to the output node of the first latch. A read/write (R/W) circuit includes a plurality of transistors coupling a word line, a bit line, and an inverted bit line to at least two outputs. One of the at least two outputs is coupled to the input node of the first latch and another of the outputs is coupled to the input node of the second latch.

Circuit structure and related method for radiation resistant memory cell

A disclosed sense circuit for a memory circuit includes sense amplifiers that detect differences in voltage levels on complementary bitlines during read operations. Instead of the sense amplifiers having built-in footer devices that lead to significant leakage, the sense circuit incorporates a common footer device for all sense amplifiers. To ensure that this footer device has sufficient drive strength to enable voltage differential detection by each sense amplifier, the sense circuit also includes a sense signal generation and boost circuit (SSG&B circuit) that generates a sense mode control signal (SEN) to control the on/off states of the footer device and that further boosts SEN, at the appropriate time, to increase the drive current. By using the common footer device and the SSG&B circuit, leakage from the sense circuit is reduced during a pre-charge operation mode without sacrificing performance during a read operation mode. Also disclosed are associated method embodiments.

Low-leakage sense circuit, memory circuit incorporating the low-leakage sense circuit, and method

A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate. The first transistor and a second transistor are formed on the semiconductor substrate. Each transistor comprises a source, a drain, and a gate. The gate of the first transistor extends longitudinally as part of a first linear strip and the gate of the second transistor extends longitudinally as part of the second linear strip parallel to and spaced apart from the first linear strip. A first CB layer forms a local interconnect layer electrically connected to the gate of the first transistor. A second CB layer forms a local interconnect layer electrically connected to the gate of the second transistor. A CA layer forms a local interconnect layer extending longitudinally between a first end and a second end of the CA layer. The CA layer is electrically connected to the first and second CB layers. The first CB layer is electrically connected adjacent the first end of the CA layer and the second layer is electrically connected adjacent the second end of the CA layer. The first CB layer, the second CB layer and the CA layer are disposed between a first metal layer and the semiconductor substrate. The first metal layer being disposed above each source, each drain, and each gate of the first and second transistors. The CA layer extends substantially parallel to the first and second linear strips and is substantially perpendicular to the first and second CB layers. At least one via selectively provides an electrical connection between the CA or CB layers and the at least one metal layer.

A single-rail memory circuit includes an array of memory cells arranged in rows and columns and peripheral circuitry connected to the array for facilitating read and write operations with respect to selected memory cells. The peripheral circuitry includes, but is not limited to, boost circuits for the rows. Each boost circuit is connected to a wordline for a row and to a discrete voltage supply line for the same row. Each boost circuit for a row is configured to increase the voltage levels on the wordline and the voltage supply line for the row during a read of any selected memory cell within the row. Increasing the voltage levels on the wordline and on the voltage supply line during the read operation effectively boosts the read current. A method of operating the memory circuit reduces the probability of a read fail.

Single-rail memory circuit with row-specific voltage supply lines and boost circuits

Growing community of inventors

Cupertino, CA, United States of America

Mahbub Rashed