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Mahadevaiyer Krishnan

Donald Francis Canaperi

Michael F Lofaro

James Anthony Tornello

Tatsuya Yamanaka

Dinesh Kumar Penigalapati

Kevin Shawn Petrarca

Richard Paul Volant

Timothy Joseph Dalton

John Michael Cotte

Kenneth Jay Stein

Rangarajan Jagannathan

Randolph F Knarr

Sean P E Smith

Christian Lavoie

Judith Marie Rubino

Michael A Cobb

Dinesh R Koli

Hariklia Deligianni

Sandra Guy Malhotra

Renee Tong Mo

Shyng-Tsong Chen

Panayotis Constantinou Andricacos

Jay William Strane

Wei-Tsu Tseng

Tomohisa Konno

Jason E Cummings

David Lee Rath

Carlos Juan Sambucetti

Michael Straight Hibbs

John C Collins

Steven Erik Steen

Rebecca D Mih

Kenneth M Davis

John M Papalia

Stephen W Bedell

Daniel C Edelstein

Balasubramanian Pranatharthiharan

Jeehwan Kim

Sampath Purushothaman

Cyril Cabral, Jr

Katherine Lynn Saenger

Christopher Vincent Jahnes

Stephen McConnell Gates

Eugene John O'Sullivan

Supratik Guha

Andrew Herbert Simon

Teodor Krassimirov Todorov

Talia S Gershon

Chandrasekhar Narayan

Eric Jeffrey White

Kaushik Arun Kumar

William J Cote

Chao-Kun Hu

Sunfei Fang

Darryl D Restaino

John Harold Magerlein

John Gerard Gaudiello

Satya Venkata Nitta

Satyavolu S Papa Rao

Balasubramanian S Pranatharthi Haran

Maurice McGlashan-Powell

George Gabriel Totir

Jennifer L Lund

Horatio Seymour Wildman

Dennis G Manzer

Byungha Shin

Fen Fen Jamin

Steffen K Kaldor

James Edward Fluegel

Richard O Henry

Michael Joseph MacDonald

Takashi Ando

Josephine B Chang

Michael A Guillorn

Soon-Cheon Seo

Zhen Zhang

Stephen Mark Rossnagel

Robert L Bruce

James Gardner Ryan

Max Gerald Levy

Gregory Costrini

John Patrick Hummel

Laura Louise Kosbar

Cuc Kim Huynh

Matthew J Sendelbach

Joyce C Liu

Clifford Owen Morgan, Iii

Paul M Feeney

Xiaomeng Chen

William C Wille

Scott Alan Estes

Philippe M Vereecken

Michael T Brigham

Kia-Seng Low

Terrance M Wright

Philip Murphy

Sol Krongelb

Mark P Murray

Edward Jack Gordon

A semiconductor device structure and method for forming the same is disclosed. The structure incudes a silicon substrate having at least one trench disposed therein. An electrical and ionic insulating layer is disposed over at least a top surface of the substrate. A plurality of energy storage device layers is formed within the one trench. The plurality of layers includes at least a cathode-based active electrode having a thickness of, for example, at least 100 nm and an internal resistance of, for example, less than 50 Ohms/cm. The method includes forming at least one trench in a silicon substrate. An electrical and ionic insulating layer(s) is formed and disposed over at least a top surface of the silicon substrate. A plurality of energy storage device layers is formed within the trench. Each layer of the plurality of energy storage device layers is independently processed and integrated into the trench.

Fabrication of all-solid-state energy storage devices

A method for forming a semiconductor includes forming at least one trench in a silicon substrate. The at least one trench provides an energy storage device containment feature. An electrical and ionic insulating layer(s) is formed on a top surface of the substrate and sidewalls of the trench. A plurality of vias is formed through a base of the trench. The plurality of vias is filled with a metal material. A trench base current collector at the base of the trench and backside current collector at the backside of the substrate are formed from the metal material. These current collectors enable electric and thermal conductive planarization and device isolation through the substrate. A plurality of energy storage device layers is formed over the trench base current collector, and a topside current collector is formed over the plurality of energy storage device layers. A protective encapsulation layer may then be formed.

Through silicon via energy storage devices

A chemical mechanical planarization for indium phosphide material is provided in which at least one opening is formed within a dielectric layer located on a substrate. An indium phosphide material is epitaxially grown within the at least one opening of the dielectric layer which extends above a topmost surface of the dielectric layer. The indium phosphide material is planarized using at least one slurry composition to form coplanar surfaces of the indium phosphide material and the dielectric layer, where a slurry composition of the at least one slurry composition polishes the indium phosphide material selective to the topmost surface of the dielectric layer, and includes an abrasive, at least one pH modulator and an oxidizer, the at least one pH modulator including an acidic pH modulator, but lacks a basic pH modulator, and where the oxidizer suppresses generation of phosphine gas.

Indium phosphide smoothing and chemical mechanical planarization processes

Method for chemical mechanical planarization is provided, which includes: forming a dielectric layer containing at least one opening, the dielectric layer is located on a substrate; epitaxially growing a germanium material within the at least one opening of the dielectric layer, the germanium material extending above a topmost surface of the dielectric layer; and planarizing the germanium material using at least one slurry composition to form coplanar surfaces of the germanium material and the dielectric layer, where a slurry composition of at least one slurry composition polishes the germanium material selective to the topmost surface of the dielectric layer, and includes an abrasive, at least one pH modulator, and an oxidizer, the at least one pH modulator including an acidic pH modulator, and lacking a basic pH modulator.

Germanium smoothing and chemical mechanical planarization processes

A method for forming a photovoltaic device includes forming an absorber layer with a granular structure on a conductive layer; conformally depositing an insulating protection layer over the absorber layer to fill in between grains of the absorber layer; and planarizing the protection layer and the absorber layer. A buffer layer is formed on the absorber layer, and a top transparent conductor layer is deposited over the buffer layer.

Protective insulating layer and chemical mechanical polishing for polycrystalline thin film solar cells

A chemical mechanical planarization for a Group III arsenide material is provided in which at least one opening is formed within a dielectric layer located on a substrate. A Group III arsenide material is epitaxially grown within the at least one opening of the dielectric layer which extends above a topmost surface of the dielectric layer. The Group III arsenide material is planarized using at least one slurry composition to form coplanar surfaces of the Group III arsenide material and the dielectric layer, where a slurry composition of the at least one slurry composition polishes the Group III arsenide material selective to the topmost surface of the dielectric layer, and includes an abrasive, at least one pH modulator and an oxidizer, the at least one pH modulator including an acidic pH modulator, but lacks a basic pH modulator, and where the oxidizer suppresses generation of an arsine gas.

Group III arsenide material smoothing and chemical mechanical planarization processes

A method for formation of a segregated interfacial dopant layer at a junction between a semiconductor material and a silicide layer includes depositing a doped metal layer over the semiconductor material; annealing the doped metal layer and the semiconductor material, wherein the anneal causes a portion of the doped metal layer and a portion of the semiconductor material to react to form the silicide layer on the semiconductor material, and wherein the anneal further causes the segregated interfacial dopant layer to form between the semiconductor material and the silicide layer, the segregated interfacial dopant layer comprising dopants from the doped metal layer; and removing an unreacted portion of the doped metal layer from the silicide layer.

Implantless dopant segregation for silicide contacts

A method of texturing a surface of a crystalline silicon substrate is provided. The method includes immersing a crystalline silicon substrate into an aqueous alkaline etchant solution to form a pyramid shaped textured surface, with (111) faces exposed, on the crystalline silicon substrate. The aqueous alkaline etchant solution employed in the method of the present disclosure includes an alkaline component and a nanoparticle slurry component. Specifically, the aqueous alkaline etchant solution of the present disclosure includes 0.5 weight percent to 5 weight percent of an alkaline component and from 0.1 weight percent to 5 weight percent of a nanoparticle slurry on a dry basis.

Silicon surface texturing method for reducing surface reflectance

A reticle carrier for a polishing tool capable of accommodating a reticle includes a base plate with an obverse and reverse surfaces, a retaining ring secured to the obverse surface of the base plate forming a recess defined by the obverse surface of the rigid base plate and internal edges of the retaining ring. A reticle pad supports a reticle in the recess. The base plate and the reticle pad having an array of matching, aligned passageway holes therethrough for exhaustion of air from space between the base plate and a the reticle and for supply of air to that space so a vacuum can retain a the reticle in place on the reticle carrier under vacuum conditions and application of air under pressure can eject a reticle from the reticle carrier.

Reticle carrier

An apparatus for chemical mechanical planarization includes a spindle assembly structure and at least one substrate carrier, which make a linear lateral movement relative to each other while abrasive surfaces of a plurality of cylindrical spindles in the spindle assembly structure contact, and rotate against, at least one substrate mounted on the at least one substrate carrier. The direction of the linear lateral movement is within the plane that tangentially contacts the plurality of cylindrical spindles, and can be orthogonal to the axes of rotation of the plurality of cylindrical spindles.

Multi-spindle chemical mechanical planarization tool

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Hopewell Junction, NY, United States of America

Mahadevaiyer Krishnan