Telefonaktiebolaget Lm Ericsson (publ)

Ericsson Modems Sa

Magnus Malmberg

Michael Breschel

Robert Wolfgang Klang

Jerker Örjmark

Kent Inge Ingesson

Torbjörn Wigren

Bo Göransson

Mattias Andersson

Sara Sandberg

Magnus Nilsson

Jonas B Karlsson

Toni Viki Brkic

Amirpasha Shirazinia

Philip Mansson

Roger Persson

Alberth Arvidsson

Philip M&aring;nsson

Joakim Ahlgren

Christel Bergh

Satbinder Singh Ram

Jerker ÖRjmark

An Advanced Antenna System (AAS) receiver and related methods are provided. According to one aspect an AAS receiver comprises a digital processing block of a Radio Frequency Integrated Circuit (RFIC). The digital processing block comprises an interface for communicating with a Central Unit (CU), and a plurality of Antenna Signal Processing Blocks (ASPBs), each receiving a digitized receive signal from a respective antenna element of an antenna array. Each ASPB comprises one or more receivers, each of which receives and processes the signal from the respective antenna element. Some receivers within the ASPB beamform the respective processed signal to produce one or more data streams to be sent to the CU. Other receivers within the ASPB provide the respective processed signal to a processing block that buffers the processed signal and sends it to the CU at a later time, e.g., when traffic to the CU is relatively lower.

Narrowband AAS receiver with data replay interfacing

According to certain embodiments, a method is provided for fast layered decoding for Low-density Parity-Check (LDPC) codes with a Parity-Check Matrix (PCM) that includes at least a first layer and a second layer. The method includes reading, from a memory, Variable Node (VN) soft information, wherein the VN soft information is associated with a message from a VN to a Check Node (CN) of the second layer of the PCM. A new CN to VN message is calculated from the CN of the second layer of the PCM. New VN soft information is calculated for the VN. The new VN soft information is calculated based on the VN soft information and a new CN to VN message from a CN of the first layer to the VN and an old CN to VN message from the CN of the first layer to the VN such that the updating of new VN soft information is delayed by at least one layer. The fast layered decoding has lower decoding latency and utilizes the decoding hardware more efficiently than standard layered decoding techniques. This may be achieved by keeping the memory access and processing hardware units active simultaneously to avoid excess decoding latency. More specifically, certain embodiments may carry out memory access and computation process simultaneously, without any effort to make the row layers mutually orthogonal to each other. Another technical advantage may be that the proposed decoding algorithm adjusts the LLRs to partially account for deviations from the layered decoding due to non-orthogonal rows.

Systems and methods for fast layered decoding for low-density parity-check (LDPC) codes

Systems and methods related to hardware controlled power domains in a hardware system (e.g., an integrated circuit) are disclosed. In one embodiment, fully automatic power on and power off of the power domains in the hardware system is provided without software involvement. In this manner, power up and power down times for the power domains are substantially reduced or minimized, which in turn enables shorter active times for the power domains and thus reduced power consumption (e.g., reduced leakage when hardware in the power domains is idle).

HW-controlled power domains with automatic power-on request

Generic devices, systems and methods for multiple radio access technologies (RATs) are described. Arrangements can include, for example, a processor configured to execute procedures associated with different radio access technologies (RATs), a radio planner function configured to receive requests for radio resources from the procedures and further configured to selectively grant or deny radio access by the procedures in response to the requests, and a memory device configured to operate as a distributed data base to store data produced by at least one of the procedures and to provide the data to at least one other of the procedures.

Methods and systems for a generic multi-radio access technology

An interface module for a logic circuit block comprising a processing module, the interface module comprising a control interface for communicating one or more control messages; a data interface for accessing a data storage device; an interface logic block; and a core interface to the processing module, the core interface being connected to the interface logic block for communicating signals between the interface logic block and the processing module. The interface logic block is adapted to receive one or more incoming control message via the control interface; process the one or more control messages including accessing a data storage device via the data interface, initiating processing by the processing module via the core interface, receiving one or more signals from the processing module via the core interface; and to output one or more outgoing control message via the control interface.

Interface module for HW block

Generic devices, systems and methods for multiple radio access technologies (RATs) are described. An arrangement can include, for example, a multiple radio access technology (RAT) platform configured to enable communications with a plurality of different RATs using procedures associated with transceiver processing functions, wherein the procedures implement the transceiver processing functions through functional units (FUs) which perform operations, the FUs being implemented in at least one of hardware and software; and wherein the FUs are configured by functional unit descriptors (FUDs) which instruct an FU regarding at least one of: (a) from which memory location to fetch data to operate upon or parameters associated with an operation to be performed by the FU, (b) to which memory location to store data as a result of an operation and (c) a message type to output after the operation.

Generic devices, systems and methods for multiple radio access technologies (RATs) are described. A platform for allocating radio resources among a plurality of radio access technology (RAT) modules can include, for example, radio hardware configured to transmit and receive radio signals over an air interface using the plurality of RATs; and a radio planner connected to the radio hardware and configured to receive radio time reservation requests, each of which requests includes a priority value for the radio time reservation request, and to determine whether to grant or deny each of the radio time reservation requests based at least in part on the priority values.

Debug circuitry is operated in a manner that facilitates debugging one or more hardware and/or software components that are included in a system that includes a system memory. The debug circuitry receives information from one of the hardware and/or software components and/or from the system memory, and ascertains whether the received information includes memory address parameters. If the received information includes memory address parameters, then the memory address parameters are used to retrieve data from the system memory. The retrieved data is supplied at an output port of the debug circuitry.

Hardware/software debugging using memory access parameters

A Reduced-State Sequence Estimation (RSSE) method is disclosed, whereby states in a trellis structure associated, for example, with a Viterbi algorithm are partitioned into a plurality of hyper-states. During a hyper-state decision interval, a hyper-soft value is calculated. The calculated hyper-soft value is a measurement of the accuracy of the hyper-state decision made. The calculated hyper-soft value can be used by an equalizer to generate soft-value information for decoding. A soft-value generated from such a hyper-soft value combined with bit soft-value in an RSSE algorithm is significantly more accurate than a soft-value that can be generated for a DFSE algorithm (i.e., without such a hyper-soft value).

Growing community of inventors

Södra Sandby, Sweden

Magnus Malmberg