Texas Instruments Corporation

Magnus G Karlsson

Gregory Lee Christison

Norayda Humphrey

Michael J Moody

The present invention provides an apparatus, system and method for transmitting asynchronous transfer mode (ATM) data cells on an ATM adaptation layer (AAL) configured connection within an ATM system comprising a digital signal processor (DSP) sub-system () and a host processor (). The transmitter interfaces directly with the DSP sub-system () (which converts the digitized voice samples into voice signals) and the host processor () (which performs AAL2 signaling and layer management functions). The transmitter is configured to interleave AAL2 voice packets from the DSP sub-system () and signaling and management packets from the host processor () on an ATM connection. Data is fetched by DMA(s) (). A channel look-up table uses the DSP assigned voice channel as an index into the table to map a voice channel to the ATM connection.

AAL2 transmitter for voice-packed and signaling management-packed interleaving on an ATM connection

A Universal Serial Bus (USB) modem () in which reassembly and segmentation operations are performed outside of the host computer () is disclosed. A USB interface device () is coupled to a digital signal processor (DSP) () in the modem (), and contains a shared memory () in which bulk endpoints () are established, at which received ATM cell payload data may be stored. An ATM receive controller () is provided in the USB interface device (), which receives each ATM cell from the DSP () and interrogates the ATM cell header to determine which, if any, virtual connection the cell corresponds. The ATM receive controller () then forwards the payload portion of the ATM cell, but not the ATM cell header, to the endpoint () corresponding to the virtual connection to which the ATM cell is directed. The disclosed ATM receive controller () also includes logic () for calculating a cyclic redundancy check value over the payload portion of the ATM cells that make up an ATM packet.

Hardware acceleration for reassembly of message packets in a universal serial bus peripheral device

The present invention provides a unitary mechanism for high speed end-to-end telecommunication traffic using an Asynchronous Transfer Mode (ATM) architecture for convergence of video, data and voice in an SOHO application using a DSL router. An ATM module () for convergence of the telecommunications traffic includes an ATM processor () configured to perform QoS, OAM processing and switching in an ATM system. Function modules () and data ports () are configurable to transceive data, voice and video traffic in which the traffic is packetized in ATM data cells.

ATM system architecture for the convergence of data, voice and video

The present invention provides an apparatus, system and method for receiving asynchronous transfer mode (ATM) data cells on an ATM adaptation layer (AAL) configured connection within an ATM system comprising a digital signal processor (DSP) sub-system () and a host processor (). The receiver interfaces directly with the DSP sub-system () (which converts the digitized voice samples into voice signals) and the host processor () (which performs AAL2 signaling and layer management functions). The receiver filters the AAL2 signaling and management packets from the AAL2 voice packets using a host programmable CID filter () and UUI filter (). A match from either filter () enables the packet to be forwarded to the host processor (). If no match is made in either filter (), then a look-up is performed in a receive CID look-up table and the packet is forwarded to the DSP sub-system () on a look-up match.

AAL2 receiver for filtering signaling/management packets in an ATM system

The present invention provides an apparatus and system for high speed end-to-end telecommunication traffic using an Asynchronous Transfer Mode (ATM) architecture for convergence of video, data and voice in an SOHO application using a DSL router. An ATM processor () enables traffic shaping, and operation and maintenance processing within a single module. The ATM processor () further includes a processor () which executes firmware from a program memory (). A register block () is provided for communicating setup and teardown notification, and OAM configuration to the processor () and a connection state RAM () provides for communicating connection configuration in which this information is used by the processor () when performing the functions of switching, QoS, and OAM. Transmit scheduler hardware () is provided for the scheduling of ATM cell transmission and is configured by the processor ().

ATM processor for switching in an ATM system

The present invention provides an apparatus and system for buffering data in a communication network with an arranged priority which enables traffic shaping. A cell buffer unit () is arranged with a plurality of queues () configured to store PDUs on-chip and off-chip. There are associated queues both on-chip and off-chip for each priority queue. A cell buffer controller () forwards PDUs to a predetermined priority queue and manages the transfer of PDUs off-chip when a priority queue on-chip is fully occupied. The controller () also manages the transfer of PDUs from the off-chip queue when the on-chip priority queue becomes less than fully occupied.

Cell buffering system with priority cache in an ATM system

A Universal Serial Bus (USB) modem ( ) in which reassembly and segmentation operations are performed outside of the host computer ( ) is disclosed. A USB interface device ( ) is coupled to a digital signal processor (DSP) ( ) in the modem ( ), and contains a shared memory ( ) in which bulk endpoints ( ) are established, at which ATM packet header and payload data are stored prior to transmission. An ATM transmit controller ( ) retrieves the header portion of the ATM packet from a transmit endpoint ( ) and stores the information in registers ( ) in the ATM transmit controller ( ). A four-byte ATM cell header is then transmitted to byte buffers ( ) and to the DSP ( ) for transmission over the communications facility. Afterwards, payload data is retrieved from the transmit endpoint ( ) in shared memory ( ), and forwarded to byte buffers ( ) for transmission.

Hardware acceleration for segmentation of message packets in a universal serial bus peripheral device

A Universal Serial Bus (USB) modem ( ) having two operating modes, namely Digital Subscriber Loop (DSL) mode and a voice-band mode, is disclosed. A USB interface device ( ) is coupled to a digital signal processor (DSP) ( ) and contains a shared memory ( ) in which USB endpoints are established for data communication. In the DSL mode, an ATM receive controller ( ) receives each ATM cell from the DSP ( ) and interrogates the ATM cell header to determine the virtual connection to the corresponding cell, and then forwards the payload portion of the ATM cell, but not the ATM cell header. In the voice-band mode, the ATM receive controller ( ) and ATM transmit controller ( ) operate in a simple streaming mode. A host interface controller ( ) is also provided, by way of which facsimile communications are carried out simultaneously with DSL communications, or in separate sessions relative to voice-band data communications.

Hybrid digital subscriber loop and voice-band universal serial bus modem

A USB function device ( ) for coupling to a USB host ( ). The USB function device ( ), comprises circuitry ( ) for providing a capability to the USB host, where the circuitry for the capability comprises an address space. The USB function device further comprises a USB interface circuit ( ) coupled between the USB host ( ) and the circuitry ( ) for providing a capability to the USB host. The USB interface circuit comprises a memory area ( ) comprising a code overlay endpoint ( ) accessible to the USB host for writing two or more code blocks to the code overlay endpoint. The USB interface circuit further comprises circuitry ( ) for communicating a first of the code blocks from the code overlay endpoint to the address space and for subsequently communicating a second of the code blocks from the code overlay endpoint to the address space. The circuitry for communicating is operable to communicate a code block from the code overlay endpoint to the address space after a start-up time of the USB function device.

Architecture enabling code overlay using a dedicated endpoint

A USB function device ( ) for coupling to a USB host ( ). The USB function device ( ) comprises circuitry ( ) for providing a capability to the USB host, where the circuitry for providing a capability comprises an address space (VBUS). The USB function device ( ) further comprises a USB interface circuit ( ) coupled between the USB host and the circuitry for providing a capability to the USB host. The USB interface circuit ( ) comprises a memory area ( ) comprising a write endpoint ( ) accessible to the USB host for writing a plurality of bytes to the memory area via the write endpoint. The plurality of bytes comprise data information and protocol information. The write endpoint comprises an endpoint-type other than a control-type endpoint. The USB interface circuit also comprises circuitry for decoding ( ) the protocol information and circuitry for communicating the data information to the address space in response to the protocol information.

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McKinney, TX, United States of America

Magnus G Karlsson