Broadcom Corporation

Avago Technologies International Sales Pte. Limited

Other

Avago Technologies General IP (Singapore) Pte. Ltd.

Magesh Valliappan

Afshin Momtaz

Namik Kocaman

Adam Benjamin Healey

Vivek Telang

Velu Pillai

Sundararajan Chidambara

Anand Kumar Pathak

Howard A Baumer

John James Paulos

Eric Kimball

Vasudevan Parthasarathy

Bruce Howard Conway

James Francis McElwee

Sameer Kanhaiyalal Shah

Vivek Venkatraman

Lin Zheng

Anthony Brewster

A digital signal processing (DSP)-based serializer-deserializer (SERDES) includes a first filter configured to mitigate inter-symbol interference (ISI) attributed to dispersion associated with a long-reach transmission medium. The SERDES includes a second filter configured to shape the ISI. The SERDES includes also includes a third filter coupled in parallel with the second filter and configured to reduce ISI attributed to reflections associated to both near-zero delays and long delays.

Efficient architecture for high-performance DSP-based long-reach SERDES

A digital signal processing (DSP) device includes a first fitter to equalize channel dispersion associated with signal transmission through a medium, a second filter to cancel channel reflections, and a third filter to at least reduce noise. The DSP device is a receiver DSP of the SERDES.

Efficient architecture for high-performance DSP-based SERDES

The present disclosure is directed to systems, apparatuses, and methods for performing continuous or periodic link training. Existing link training protocols generally perform link training only once during startup or initialization of a link and, as a result, are limited in their applications. After link training is performed and Open Systems Interconnect (OSI) data link layer and other high-layer data is transmitted across the link, no further link training is performed using these existing link training protocols. However, parameters of the link may change over time after link training is performed, such as temperature of the link and voltage levels of signals transmitted over the link by the transmitter of the transmitter-receiver pair.

High-speed interconnect solutions with support for secondary continuous time in-band back channel communication for simplex retimer solutions

An electronic device includes circuitry configured to establish a steady-state connection with another device via a communication link. A backchannel data frame is detected in a steady-state data stream received from the other device via the communication link at a first predetermined data rate. The circuitry is configured to modify one or more signal transmission parameters based on signal information included in the backchannel data frame.

Backchannel protocol for link training and adaptation

A device for transmit (TX) training a remote link partner (LP) includes a TX retimer module adjacent to a TX port of the device, and a receive (RX) retimer module adjacent to the TX retimer module. The RX retimer module copies first control and status data to the TX retimer module, and the TX retimer module provides second control and status data for TX training of the remote LP.

Remote TX training with a re-timer

Embodiments of the present disclosure provide an in-band process to inform an external repeater of a desired new configuration or mode of operation. After negotiation of rate and other information during an auto-negotiation routine, a network node sends configuration information to a network element, such as an external network repeater.

Automatic configuration of a repeater

A switch device can identify when a loss of signal event occurs on a communication link connecting a local link partner and a remote link partner. The switch device may automatically perform a link restart process to restore communication with the remote link partner without performing a speed negotiation with the remote link partner. The link restart process may include disabling a transmitter for a recovery duration and configuring a transmitter and a receiver to an initial configuration state. The link restart process may also synchronize the start of a training protocol communication between the local link partner and remote link partner. The switch device may also perform the link restart process when traffic received from the remote link partner fails a link criteria.

Automatic recover after loss of signal event in a network device

Reference-less repeating circuits provide significant advantages over repeating circuits requiring external frequency references. These repeating circuits eliminate the need for external frequency references provide significant power, layout, and physical isolation advantages. Digitally controlled reference-less repeating circuits have a relatively narrow frequency detection range, but typically consume significantly less power than analog repeating circuits while providing data rate flexibility, particularly at lower data rates. Due to the narrow frequency detection range of digitally controlled reference-less repeating circuits, efficient frequency estimation techniques allow these circuits to quickly lock to an input signal, and provide an accurate repeated output signal.

Method and apparatus for reference-less repeater with digital control

An apparatus and method is disclosed to compensate for one or more offsets in a communications signal. A communications receiver may carry out an offset adjustment algorithm to compensate for the one or more offsets. An initial search procedure determines one or more signal metric maps for one or more selected offset adjustment corrections from the one or more offset adjustment corrections. The offset adjustment algorithm determines one or more optimal points for one or more selected offset adjustment correction based upon the one or more signal maps. The adaptive offset algorithm adjusts each of the one or more selected offset adjustment corrections to their respective optimal points and/or each of one or more non-selected offset adjustment corrections to a corresponding one of a plurality of possible offset corrections to provide one or more adjusted offset adjustment corrections. A tracking mode procedure optimizes the one or more adjusted offset adjustment corrections.

Adaptive offset adjustment algorithm

A method and a system for accurately calculating the timing margin in a clock and data recovery system (CDR) is provided that utilizes a singular path environment of hardware. The method entails adding an amount of jitter within the CDR to change the receiver phase. The amount of jitter is incrementally increased until a threshold level of bit errors occur. Based on the amount of jitter needed to cause the threshold level of bit errors, timing margin can be calculated.

Apparatus and method to measure timing margin in clock and data recovery system utilizing a jitter stressor

Various embodiments are disclosed relating to crosstalk emission management. In an example embodiment, an amplitude of a main tap of a transmit equalizer may be determined to limit crosstalk emitted from a local channel to one or more other channels to be less than a threshold. A ratio of an amplitude of at least one secondary tap of the transmit equalizer to the amplitude of the main tap may be determined to provide equalization to the local channel.

Crosstalk emission management

According to an example embodiment, an apparatus may include logic. The apparatus may be configured to: determine, based on an error location polynomial, an error location syndrome corresponding to an actual location of a burst error in a data block; select a burst error pattern that is less than or equal to M bits, and having no more than Y consecutive zeros within the burst error, where M is greater than the order of the error location polynomial; determine an error pattern syndrome based on the selected burst error pattern and the error location polynomial; and determine an actual location of the burst error in the data block based on the error location syndrome and the error pattern syndrome.

Burst error correction based on fire code

GBit/s transceiver with built-in self test features. A method is disclosed for testing the operation of a transceiver having a digital processing section and an analog section, each having a transmit portion and a receive portion, the analog portions adaptable to interface with an analog network. The transceiver is first configured to operate in a test mode. In the test mode, the transmit portion of the digital processing section is activated to generate data to be transmitted by the transmit portion of the analog section. The receive portion of the analog section and the receive portion of the digital processing section are operated to receive data. Thereafter, the parametrics of select portions of the receive portion of the digital processing section are examined during the receipt of data by the receive portion of the analog section and processing thereof by the receive portion of the digital processing section.

Growing community of inventors

Austin, TX, United States of America

Magesh Valliappan