Qualcomm Incorporated

Magesh Hariharan

Hans Georg Gruber

Julio Arceo

Suren Mohan

Mark A Landguth

Peter J Shah

Aris Balatsos

Bengt Stefan Gustavsson

Siva Pavan Kumar Mitnala

John Michael Murray

A method includes sending data from a first serial low-power inter-chip media bus (SLIMbus) component to a second SLIMbus component. The method further includes sending the data via at least a first SLIMbus data line of a plurality of SLIMbus data lines.

System and method of sending data via a plurality of data lines on a bus

A particular apparatus includes a coder/decoder (CODEC) including a first processor and a first buffer. The first processor is configured to analyze audio data samples to detect a keyword. The CODEC is configured to store a set of audio data samples at the first buffer. The apparatus also includes an application processor configured to receive the set of audio data samples from the CODEC via a bus and configured to initialize a speech recognition engine (SRE) based on the set of audio data samples. The application processor is configured to initialize the bus based on an indication from the CODEC that the keyword is detected.

System and method of analyzing audio data samples associated with speech recognition

Methods, systems, apparatuses, and computer-readable media for controlling components connected to and/or otherwise associated with a data bus are presented. According to one or more aspects of the disclosure, a plurality of processing devices having data bus management capability and at least one data bus associated with the plurality of processing devices may be identified. Subsequently, an inter-processor communication (IPC) layer for communication between the plurality of processing devices and the at least one data bus may be established over a messaging layer utilized by the at least one data bus. At least one component associated with the at least one data bus may then be controlled via the IPC layer using at least one of the plurality of processing devices.

Multiple slimbus controllers for slimbus components

Arrangements for restarting data transmission on a serial low-power inter-chip media bus (SLIMbus) are presented. A clock signal may be provided in an active mode to a component communicatively coupled with the SLIMbus. Immediately prior to the clock signal in the active mode being provided, the clock signal may have been in a paused mode. While the clock signal was in the paused mode at least until the clock signal is provided in the active mode, the data line may have been inactive (e.g., a toggle on the data line may not have been present). Frame synchronization data for a frame may be transmitted. The frame synchronization data for the frame, as received by the component, may not match expected frame synchronization data. Payload data may be transmitted as part of the frame to the component, wherein the payload data is expected to be read properly by the component.

Methods, systems, apparatuses, and computer-readable media for waking a SLIMbus without toggle signal

Techniques are disclosed for utilizing a non-ported generic device (NGD) or other non-ported hardware to couple processing device(s) to access components on a serial data bus without the need for integrated manager hardware. Using the NGD, a processing device(s) can utilize available unused bandwidth on the serial data bus to communicate with components coupled with the serial data bus, including a processing device having the manager hardware. Various alterations and embodiments are disclosed.

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San Diego, CA, United States of America

Magesh Hariharan