Raytheon Company

Magathi Willis

Micky R Harris

An interface BIT failure detection circuit includes a sequencing circuit and a multiplexer. The sequencing circuit configured to generate the sequence selection signal. The multiplexer is in signal communication with the sequencing circuit, and includes a plurality of interface input. Each interface input corresponds to an interface of a device under test. The sequence selection signal is configured to control the MUX to sequentially select each of the interface inputs. The MUX includes an output terminal configured to output a test signal configured to indicate whether or not at least one fault corresponding to one or more of the interface inputs or a main power supply exists.

Interface built in test failure detection apparatus

A configurable driver is presented, comprising: a first transistor of a first type coupled to a first node; a second transistor of the first type coupled to a second node; a first transistor of a second type coupled to the first node; a second transistor of a second type coupled to the second node; a first multiplexer coupled to a gate of the first transistor of the first type; a second multiplexer coupled to a gate of the second transistor of the first type; a third multiplexer coupled to a gate of the first transistor of the second type; a fourth multiplexer coupled to a gate of the second transistor of the second type; and one or more switching devices coupled between the first node and the second node.

Channel based configurable CML, LVDS, open drain output

A system for automatically calibrating a phase locked loop (PLL), the system comprising: a node a voltage controlled oscillator (VCO) coupled to the node and configured to provide an output signal to the node; at least one digital-to-analog converter (DAC) coupled to the VCO and configured to provide a voltage to the VCO; and at least one controller configured to: determine an output frequency of the output signal; responsive to determining the output frequency, compare the output frequency to the voltage; responsive to determining the output frequency, compare the output frequency to a target frequency; and control the DAC to modify the voltage based on a comparison of the output frequency to the voltage and a comparison of the output frequency to the target frequency.

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Broomfield, CO, United States of America

Magathi Willis