Lattice Semiconductor Corporation

Magathi Jayaram

Vinh Ho

Hamid Ghezel

Allan Lin

David Li

Qin Wei

David Wei

In one embodiment, an integrated circuit has one or more multi-channel transmitters, each transmitter having synchronization circuitry that synchronizes different copies of a reset signal used to reset different sets of TX channel circuitry used to generate the multiple TX signals, to reduce the skew between the different TX signals. Each set of synchronization circuitry has (at least) two synchronization stages that re-time different copies of the reset signal to a selected clock signal. In one implementation, the integrated circuit has (at least) two quads, each of which can generate four different TX signals, where both quads can be configured to use the same clock signal to re-time different copies of the reset signal such that the eight different TX signals are all synchronized to one another.

Multi-channel transmitter synchronization circuitry

In one embodiment, a voltage-controlled oscillator has a ring of delay stages and power-regulating circuitry regulating power to each delay stage. Each delay stage has at least one inverter having a leg having a current regulator that controls current flowing through the leg and thereby controlling gain of the delay stage. The VCO receives three control signals that affect the amount of delay applied by each delay stage and therefore the VCO output frequency: a first applied to control the power-regulating circuitry, a second applied to at least one transistor gate in the current regulator, and a third applied to at least one transistor body in the current regulator. The power-regulating circuitry has a parallel configuration of a power-regulating transistor, a first capacitor, and a switched-capacitor leg having a second capacitor and a switch for controlling settling time. The capacitors regulate the power supply without a dedicated, opamp-based voltage regulator.

High-resolution oscillator having wide frequency range

In several embodiments of the invention, a programmable architecture for FIR filters includes a tapped delay chain and a number of different slices. Each slice has a multiplexer that receives all of the tapped input-signal samples and a programmable current driver. Each slice can be independently programmed to correspond to any one of the taps in the delay chain, such that zero, one, or more slices can be associated with any of the delay-chain taps. Moreover, the current driver in each slice can be independently programmed to contribute any available driver strength level for the selected tap, where the combination of one or more drive strengths associated with a given tap corresponds to the effective tap coefficient for that tap. In this way, the architecture can be programmed to provide a variety of different filters having not just transfer functions with different coefficient values, but also transfer functions having different numbers of pre-cursor and/or post-cursor taps.

Programmable filter

In one embodiment, a hybrid output buffer having both an H-bridge mode and a CML mode of operation includes a plurality of transistor switches arranged between an upper rail and a bottom rail. A first pair of the transistor switches couples between the upper rail and respective output nodes. A pair of resistors couples between the output nodes and a central node. During H-bridge mode, the hybrid output buffer controls a potential of the upper rail responsive to a feedback signal proportional to a difference between a potential of the central node and a common-mode voltage.

Growing community of inventors

San Jose, CA, United States of America

Magathi Jayaram