Texas Instruments Corporation

Madusudanan Srinivasan Gopalan

Christopher Andrew Schell

Benyong Zhang

Arlo Jame Aude

Robert Karl Butler

Alex Wu

A clock generator circuit including an integer divider, having a first input receiving a reference clock and configured to generate an intermediate clock at a frequency divided down from a frequency of the reference clock by an integer value, a digital delay stage configured to generate a delayed intermediate clock delayed from the intermediate clock by a number of fractional cycles of the reference clock selected responsive to a fractional cycle value, and an analog delay stage configured to generate an output clock delayed from the delayed intermediate clock by a delay value selected responsive to a fine adjustment value. The clock generator circuit further includes math engine circuitry configured to compute a phase adjustment code responsive to the phase adjustment word, the phase adjustment code comprising the integer value, the fractional cycle value, and the fine adjustment value. The clock generator circuit may be implemented in a clock domain of a system along with one or more other clock generator circuits that each generate an output clock based on a reference clock generated by a reference clock source, such as a phase-locked loop.

Dynamic phase adjustment for high speed clock signals

In examples, an apparatus includes a first transistor, voltage source, resistor, second transistor, third transistor, and capacitor. The first transistor has a first gate, first source, and first drain, in which the first source is coupled to a first voltage terminal. The resistor is coupled between the first gate and the voltage source. The voltage source is coupled between the resistor and the first voltage terminal. The second transistor has a second gate, a second source, and a second drain, in which the second gate is coupled to the first drain, and the second source is coupled to the first voltage terminal. The third transistor has a third gate, a third source, and a third drain, in which the third drain is coupled to the second drain, and the third source is coupled to a ground terminal. The capacitor is coupled between the first drain and the third gate.

Level shifter

Timing alignment circuits for use in synchronizing output signals of high-speed dividers and other clock generators are provided. An example timing alignment circuit includes detection circuitry to receive first and second output signals, and output an error sign signal indicating whether the second output signal leads or lags the first output signal and a divide ratio slip signal. The example timing alignment circuit also includes control and aligning circuitry. The control circuitry receives a first local sync status signal and outputs a first control signal to a first component. The aligning circuitry receives the error sign signal and the divide ratio slip signal from the detection circuitry and also receives a second local sync status signal indicating when the first and second output signals are synchronized. The aligning circuitry outputs a second control signal to a second component that synchronously enables the output path receiving the clocks from different dividers with all rising edges aligned similar to a circuit exiting a synchronous reset.

Synchronous alignment of multiple high-speed dividers

A duty cycle correction circuit, and method of operating the same, to correct the duty cycle of an input clock signal having a frequency divided-down from a reference clock by an odd-valued integer. A delay stage outputs the input clock signal delayed by one half-cycle of the reference clock, and a logic circuit outputs an extended clock signal by a logical OR of the input and delayed clock signals. A latch latches the extended clock signal when enabled by the reference clock, and a flip-flop latches the extended clock signal responsive to the reference clock. A gate selects the latch output or the flip-flop output based on the state of the delayed clock signal as an intermediate signal. A multiplexer generates the output clock by selecting between the intermediate signal and the input clock signal in alternating reference clock phases.

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Issaquah, WA, United States of America

Madusudanan Srinivasan Gopalan