Qualcomm Incorporated

Broadcom Corporation

Madjid Hafizi

Xiaohua Kong

Jie Xu

Nam Dang

Miao Li

Arya Behzad

Zhi Zhu

Adedayo Ojo

Chiu Keung Tang

George Shing

In certain aspects, a voltage regulator includes a pass n-type field effect transistor (NFET) coupled between a first voltage rail and a second voltage rail, and a pass p-type field effect transistor (PFET) coupled between the first voltage rail and the second voltage rail. The voltage regulator also includes a first amplifier having an output, a first switch coupled between the output of the first amplifier and a gate of the pass NFET, a second amplifier having an output, and a second switch coupled between the output of the second amplifier and a gate of the pass PFET, a third switch coupled between the gate of the pass NFET and a ground, and a fourth switch coupled between the gate of the pass PFET and the second voltage rail.

Hybrid voltage regulator with a wide regulated voltage range

In certain aspects, a driver includes a pull-down transistor coupled between an output and a ground, a pull-up n-type field effect transistor (NFET) coupled between a first voltage rail and the output, and a pull-up p-type field effect transistor (PFET) coupled between the first voltage rail and the output. The driver also includes a first switch coupled between a gate of the pull-up NFET and the ground, and a second switch coupled between a gate of the pull-up PFET and a second voltage rail.

Hybrid driver with a wide output amplitude range

An in-phase/quadrature (I/Q) clock generator is described. The I/Q clock generated includes a poly-phase filter configured to generate a four-phase quadrature clock signal in response to a two-phase quadrature clock signal generated in response to a single-ended input clock signal. The I/Q clock generated also includes a phase interpolator configured to generate an output four-phase quadrature clock signal from the four-phase quadrature clock signal. The I/Q clock generated further includes a poly-phase filter tune circuit coupled to an output of the phase interpolator. The poly-phase filter tune circuit is configured to generate a control voltage for the poly-phase filter to tune the four-phase quadrature clock signal from the poly-phase filter.

Clock generation architecture using a poly-phase filter with self-correction capability

A pre-driver circuit generates a driver bias signal based on a swing command, a driver impedance characteristic, and an input signal. A driver receives the driver bias signal and generates, in response, a driver signal having a swing and having an output impedance corresponding to the bias signal. Optionally, the driver receives power from a switchable one of multiple supply rails, according to the swing. Optionally, the driver has voltage controlled resistor elements and the driver bias signal is generated based on the swing command and a replica of the driver voltage controlled resistor elements.

Multi-standard, automatic impedance controlled driver with supply regulation

A transmit driver is configured to operate under distinct supply voltage provided at output differential terminals. The transmit driver includes differential input transistors, first and second pairs of over-voltage protection differential transistors, and a current source coupled in series between the output terminals and a lower voltage rail. The transmit driver includes a first bias voltage generator configured to generate a first bias voltage based on the supply voltage across the output differential terminals. The first bias voltage is applied to the control terminals of the first pair of over-voltage protection transistors. The transmit driver includes a second bias generator for generating a second (substantially fixed) bias voltage for the control terminals of the second pair of over-voltage protection transistors. The transmit driver may be configured to operate based on a 3.3V supply voltage provided by an HDMI sink, or based on a 1.8V supply voltage provided by a bridge chip.

Apparatus and method for transmitting data signal based on different supply voltages

A transmit driver or transmitter is provided to generate an output data signal based on different input modes, such as low speed (LS), full speed (FS), high speed (HS), and high speed interconnect (HSIC) modes of a Universal Serial Bus (USB) standard. The transmit driver includes a rail voltage generator for generating a rail voltage for a set of transmit driver slices based on the selected mode. The transmit driver includes a bias voltage generator for generating a bias voltage based on the selected mode for protecting transistors in the transmit driver slices from over-voltage stress. The transmit driver includes a predriver and level shifter for generating input signals for the transmit driver slices to set the output impedance of the transmit driver and the slew rate of the output data signal. The transmit driver includes an emphasis equalizer for providing controllable emphasis equalization to the output data signal.

Apparatus and method for transmitting data signal based on various transmission modes

A voltage-mode transmitter includes a calibration circuit having a replica circuit. By adjusting a feedback voltage driving a gate of a replica transistor in the replica circuit so that an impedance of the replica circuit matches an impedance of a variable resistor, the calibration circuit calibrates an output impedance of a single slice driver.

Voltage-mode SerDes with self-calibration

A driver circuit for transmitting serial data on a communication link combines voltage-mode and current-mode drivers. The driver circuit uses a voltage-mode driver as the main output driver. One or more auxiliary current-mode drivers are connected in parallel with the voltage-mode driver to adjust the output signal by injecting currents into the outputs. The voltage-mode driver supplies most of the output drive. Thus, the output driver circuit can provide the power efficiency benefits associated with voltage-mode drivers. The current-mode drivers can provide, for example, pre-emphasis, level adjustment, skew compensation, and other modifications of the output signals. Thus, the driver circuit can also provide the signal adjustment abilities associated with current-mode drivers.

Serdes voltage-mode driver with skew correction

A distribution current is split into a first control current, a second control current, and a third control current, in an apportionment according to a distribution command. A first control voltage is generated in response to the third control current. A second control voltage is generated as indication of the first control current, and a third control voltage is generated as indication of the second control current. Optionally, de-emphasis contribution of a first driver, a second driver and a third driver to an output is controlled based, at least in part, on the first control voltage, the second control voltage and the third control voltage, respectively.

Method and apparatus for multi-level de-emphasis

A population of drivers is provided in parallel to a driver output and a population of pre-emphasis path drivers is provided in parallel to the driver output. The population of drivers is updated and the population of pre-emphasis path drivers is updated in an inverse relation to the updating of the population of pre-emphasis path drivers. Optionally, the population of drivers has an initial value of n and the population of pre-emphasis path drivers has an initial value of m, and the sum of n and m is P. Optionally, the updated population of n is n' and the updated population of m is m&#x2032;, and n&#x2032; is approximately equal to P&#x2212;m&#x2032;.

Method and apparatus for constant output impedance, variable pre-emphasis drive

Aspects of a method and system for configurable Active/Passive Mixer and Shared GM Stage may include configuring an RF mixer in frequency demodulator to operate in an active mode or a passive mode. An in-phase (I) processing path and a quadrature (Q) processing path of the RF mixer may utilize a single shared GM stage. One or more switches may be activated to enable the active mode or the passive mode of operation for the RF mixer.

Method and system for configurable active/passive mixer and shared GM stage

Aspects of a method and system for a shared GM-stage between in-phase and quadrature channels may include processing an in-phase (I) component signal for the I channel and a quadrature (Q) component signal for the Q channel via one or more shared transconductance stages in a frequency demodulator. The I channel may be isolated from the Q channel and the Q channel may be isolated from the I channel using isolation resistors. The values of the isolation resistors may be selected so as to balance the isolation and signal attenuation. A folding circuit, comprising active devices, may isolate the I channel from the Q channel. A generated voltage may be utilized to bias the folding circuit. An oscillator for the I channel may be isolated from a mixer for the Q channel and an oscillator for the Q channel may be isolated from a mixer for the I channel.

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San Diego, CA, United States of America

Madjid Hafizi