Lsi Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Madhusudan Kalluri

Shaohua Yang

Johnson Yen

Fan Zhang

Bruce Alexander Wilson

Lei Chen

Sancar Kunt Olcay

Kiran Kumar Gunnam

Yang Han

Weijun Tan

Ming Jin

Yuan Xing Lee

Wu Chang

Changyou Xu

Jefferson E Singleton

Kapil Gaba

Ngok Ying Chu

Jianqing Chen

Sathiyanarayanan Sampath Kumar

Jonseung Park

A data processing system includes a data input configured to receive input blocks of data, a memory configured to store the input blocks of data, a data processor configured to process the input blocks of data and to yield corresponding processed output blocks of data and a scheduler configured to cause the data processor to output the output blocks of data after a processing criterion has been met in the data processor. The memory is configured to retain the input blocks of data for reprocessing after the corresponding processed output blocks of data have been output from the data processor. The scheduler includes a control input configured to receive reprocessing requests for the retained input blocks of data. The scheduler is configured to initiate a reprocessing operation in the data processor for the retained blocks of data when the reprocessing requests are received on the control input.

Data processing system with retained sector reprocessing

The present invention is related to systems and methods for adaptive parameter modification in a data processing system. As one example, a system is disclosed that includes a filter calibration circuit that is operable to calculate an updated coefficient for a filter circuit using a data set pair including a converged output and a corresponding data set.

Systems and methods for enhanced accuracy NPML calibration

A method for data sequence detection includes generating a first sample stream, equalizing the first sample stream to generate a first equalized sample stream, and buffering the first equalized sample stream. The first sample stream is interpolated to generate a second sample stream. The second sample stream is equalized to generate a second equalized sample stream. In a first processing path, the samples of the buffered first equalized sample stream are filtered using a first noise predictive filter bank to generate a first set of noise sample streams. In a second parallel processing path, the samples of the buffered first equalized sample stream are interpolated using a second interpolation filter to generate an interpolated sample stream and the interpolated sample stream is filtered to generate a second set of noise sample streams. The first equalized sample stream and the second equalized sample stream are processed to generate adapted filter coefficients for the second interpolation filter. The first and second set of noise sample streams are diversity combined to generate a set of combined noise sample streams. A data sequence is detected using the set of combined noise sample streams.

Data sequence detection in band-limited channels using two stream detector architecture

In one embodiment, a reconfigurable cyclic shifter arrangement has first and second reconfigurable cyclic shifters connected in series that are each selectively and independently configurable to operate in any one of three different modes at a time. In a first mode, the reconfigurable cyclic shifter is configured as four 4&#xd7;4 cyclic shifters to cyclically shift four sets of four input values. In a second mode, the reconfigurable cyclic shifter is configured as two 8&#xd7;8 cyclic shifters to cyclically shift two sets of eight input values. In a third mode, the reconfigurable cyclic shifter is configured as one 16&#xd7;16 cyclic shifter to cyclically shift one set of 16 input values. Because the first and second reconfigurable cyclic shifters are independently configurable, there are nine different configurations of the reconfigurable cyclic shifter arrangement.

Reconfigurable cyclic shifter arrangement

Various embodiments of the present inventions provide a symbol flipping LDPC decoding system. For example, a symbol flipping data processing system is disclosed that includes a low density parity check decoder operable to decode codewords and to identify unsatisfied parity checks, a symbol flipping controller operable to change values of at least one symbol in the codewords based on the unsatisfied parity checks to assist the low density parity check decoder to decode the codewords, a scheduler operable to control a decoding and symbol flipping mode in the low density parity check decoder and the symbol flipping controller, and a hard decision queue operable to store hard decisions for converged codewords from the low density parity check decoder.

Symbol flipping LDPC decoding system

The present invention is related to systems and methods for applying a data decode algorithm to different rotations or modifications of a decoder input as part of data processing.

Systems and methods for symbol re-grouping decoding processing

Various embodiments of the present inventions are related to initialization of decoder-based filter calibration, and in particular to initially using either a detector output or unconverged data from the decoder to train filter coefficients in a noise predictive calibration engine until data sectors converge in the decoder and can be used to train filter coefficients.

Initialization for decoder-based filter calibration

Various embodiments of the present invention provide systems and methods for updating detector parameters in a data processing circuit. For example, a data processing circuit is disclosed that includes a first detector circuit, a second detector circuit, and a calibration circuit. The first detector circuit is operable to receive a first data set and to apply a data detection algorithm to the first data set, and the second detector circuit is operable to receive a second data set and to apply the data detection algorithm to the second data set. The calibration circuit is operable to calculate a data detection parameter based upon a third data set. The data detection parameter is used by the first detector circuit in applying the data detection algorithm to the first data set during a period that the data detection parameter is used by the second detector circuit in applying the data detection algorithm to the second data set.

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Sunnyvale, CA, United States of America

Madhusudan Kalluri