Samsung Electronics Co., Ltd.

Other

Madhusudan Govindarajan

Sandeep Kumar

Ankush Chowdhury

Anand Mohan Pappu

Ranjit Kumar Guntreddi

Pranjal Pandey

Anurup Saha

Pushpita Dutta

M Satya Chaitanya Chigatapu

A Complementary Metal Oxide Semiconductor (CMOS) Image Sensor (CIS), includes a pixel circuit, a VSL circuit, and an amplifier. The pixel circuit may generate a reset voltage and a signal voltage, based on a power supply connected to the pixel circuit and/or intensity of light captured by the pixel circuit. The VSL circuit may store pixel information in a pixel load based on settling a voltage at the pixel load to the signal voltage and/or set the voltage at the pixel load to a pixel reset voltage based on settling the voltage at the pixel load to the reset voltage. The amplifier may generate a voltage, based on varying a resistance at an input of the amplifier, to enable the VSL circuit to store the pixel information and/or set the voltage at the pixel load to the pixel reset voltage.

Amplifier circuit for enabling power efficient and faster pixel settling in image sensors

A method for compensating a Power Supply Rejection Ratio (PSRR) in an image sensor, the method includes receiving, by processing circuitry, at least one analog signal from an active pixels sensor (APS) array, the at least one analog signal including power supply noise, combining, by the processing circuitry, amplified power supply noise with at least one ramp signal to obtain combined power supply noise, and compensating, by the processing circuitry, the PSRR of the APS array by cancelling the power supply noise of the at least one analog signal using the combined power supply noise.

Methods and systems for increasing PSRR compensation range in an image sensor

A transconductance circuit comprises a first transistor, a second transistor, a first source-degeneration device, a second source-degeneration device, a first feedback device, and a second feedback device. The gate node of the first transistor is coupled to a source node of the second transistor via the first feedback device. The gate node of the second transistor is coupled to a source node of the second transistor via the second feedback device. The source node of the first transistor is coupled to a reference voltage via the first source-degeneration device. The source node of the second transistor is coupled to the reference voltage via the second source-degeneration device.

Highly linear low noise transconductor

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Bengaluru, India

Madhusudan Govindarajan