Cadence Design Systems, Inc.

Madhur Sharma

Arnold Ginetti

Balvinder Singh

Donald John O'Riordan

Taranjit Singh Kukal

Arnold Jean Marie Gustave Ginetti

Steven Roberts Durrill

Nikhil Gupta

Vikrant Khanna

Sutirtha Kabir

Ritabrata Bhattacharya

Abhishek Dabral

Diwakar Mohan

Disclosed are methods, systems, and articles of manufacture for characterizing an electronic design with a schematic driven extracted view. These techniques identify a schematic of an electronic design, wherein the schematic exists in one or more design fabrics. These techniques further determine an extracted model for characterizing a behavior of the electronic design based at least in part upon the schematic, determine a hierarchical level in a design fabric of the one or more design fabrics of the schematic, and characterize the electronic design with at least an extracted view.

Methods, systems, and computer program product for characterizing an electronic design with a schematic driven extracted view

Disclosed are methods, systems, and articles of manufacture for binding and annotating an electronic design with a schematic driven extracted view. These techniques identify a schematic design and an extracted view of an electronic design and bind the schematic design with the extracted view. The resulting binding information concerning binding the schematic design with the extracted view is stored in a data structure. The schematic design may be annotated with extracted view information pertaining to the extracted view based at least in part upon the binding information. A response to a user action may be automatically generated based in part or in whole upon the extracted view information or the binding information.

Methods, systems, and computer program product for binding and back annotating an electronic design with a schematic driven extracted view

Disclosed are techniques for implementing a layout-driven, multi-fabric schematic design of an electronic design. These techniques identify a multi-fabric layout spanning across multiple design fabrics and layout connectivity information and determine a device map that correlates a first set of devices in the multi-fabric layout with respective parasitic models. The device map can be identified one or more pre-existing device maps or can be constructed anew. A multi-fabric schematic can be generated by using at least the respective parasitic models and the layout connectivity information.

Methods, systems, and computer program product for implementing a layout-driven, multi-fabric schematic design

Disclosed are a method, system, and computer program product for implementing various embodiments of the methods for implementing multi-power domain digital or mixed-signal verification and low power simulation. The method or the system comprises automatically generating one or more net or terminal expression, set, or one or more overriding net or terminal expression by reading, importing, or interpreting the power data file for the electronic circuit design; identifying one or more schematics of the electronic circuit design; generating an annotated schematic of the electronic circuit design by automatically annotating at least one of the one or more schematics with some of the one or more net or terminal expression, set, or one or more overriding net or terminal expression; and performing verification of the electronic circuit design by using at least the annotated schematic.

Method, system, and computer program product for implementing multi-power domain digital / mixed signal verification and low power simulation

Method, system, and computer program product for implementing multi-power domain digital / mixed-signal verification and low power simulation

Growing community of inventors

Ghaziabad, India

Madhur Sharma