Applied Materials, Inc.

Micro Materials Inc.

Madhur Sachan

Regina Germanie Freed

Mark Joseph Saly

Bhaskar Jyoti Bhuyan

Lakmal Charidu Kalutarage

Susmit Singha Roy

Kelvin Chan

He Ren

Thomas Knisley

Uday Mitra

David Michael Thompson

Swaminathan T Srinivasan

Ho-yung David Hwang

Amrita B Mullick

Yuqiong Dai

Lili Feng

Sanjay S Natarajan

El Mehdi Bazizi

Angada Bangalore Sachid

Russell Chin Yee Teo

Hoyung David Hwang

Sushant Mittal

Gabriela Alva

Yuriy Shusterman

Embodiments disclosed herein include a method of developing a metal oxo photoresist with a non-wet process. In an embodiment, the method comprises providing a substrate with the metal oxo photoresist into a chamber. In an embodiment, the metal oxo photoresist comprises exposed regions and unexposed regions, and the unexposed regions comprise a higher carbon concentration than the exposed regions. In an embodiment, the method further comprises flowing a gas into the chamber, wherein the gas reacts with the unexposed regions to produce a volatile byproduct.

Dry develop process of photoresist

Embodiments disclosed herein include methods of depositing a metal oxo photoresist using dry deposition processes. In an embodiment, the method comprises forming a first metal oxo film on the substrate with a first vapor phase process including a first metal precursor vapor and a first oxidant vapor, and forming a second metal oxo film over the first metal oxo film with a second vapor phase process including a second metal precursor vapor and a second oxidant vapor.

Deposition of semiconductor integration films

Embodiments disclosed herein include methods of developing a metal oxo photoresist. In an embodiment, the method comprises providing a substrate with the metal oxo photoresist into a vacuum chamber, where the metal oxo photoresist comprises exposed regions and unexposed regions. In an embodiment, the unexposed regions comprise a higher carbon concentration than the exposed regions. The method may further comprise vaporizing a halogenating agent into the vacuum chamber, where the halogenating agent reacts with either the unexposed regions or the exposed regions to produce a volatile byproduct. In an embodiment, the method may further comprise purging the vacuum chamber.

Vapor phase thermal etch solutions for metal oxo photoresists

A method for forming a nanostructure on a substrate includes performing a first lithography-and-etch process, including patterning a mandrel layer disposed on a first dielectric layer, performing a spacer patterning process, including forming a spacer layer on sidewalls of the patterned mandrel layer, performing a first gap-filling process, including forming a gap-filling layer in openings of the spacer layer on the first dielectric layer and over the patterned mandrel layer, performing a second lithography-and-etch process, including patterning the gap-filling layer and further patterning the patterned mandrel layer, performing a second gap-filling process, including further forming the gap-filling layer in openings of the twice patterned mandrel layer, and performing a spacer removing process, including removing the patterned spacer layer and the twice patterned mandrel layer.

Self aligned multiple patterning

Apparatuses and methods to provide fully self-aligned first metallization lines, M1, via, and second metallization lines, M2, are described. A first metallization line comprises a set of first conductive lines extending along a first direction on a first insulating layer on a substrate; a second metallization line comprising a set of second conductive lines on an etch stop layer above the first metallization line, the set of second conductive lines extending along a second direction that crosses the first direction at an angle; and at least one via between the first metallization line and the second metallization line, the at least one via comprising a via metallization layer, wherein the at least one via is self-aligned along the second direction to one of the first metallization lines and the at least one via is self-aligned along the first direction to one of the second metallization lines, the second direction crossing the first direction at an angle.

Fully self-aligned subtractive etch

Apparatuses and methods to provide a fully self-aligned via are described. A first metallization layer comprises a set of first conductive lines extending along a first direction on a first insulating layer on a substrate, the set of first conductive lines recessed below a top portion of the first insulating layer. A capping layer is on the first insulating layer, and a second insulating layer is on the capping layer. A second metallization layer comprises a set of second conductive lines on the second insulating layer and on a third insulating layer above the first metallization layer. The set of second conductive lines extend along a second direction that crosses the first direction at an angle. At least one via is between the first metallization layer and the second metallization layer. The via is self-aligned along the second direction to one of the first conductive lines. The tapering angle of the via opening may be in a range of from about 60&#xb0; to about 120&#xb0;.

Fully self-aligned via

Methods of forming and processing semiconductor devices which utilize a three-color process are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications. More particularly, certain embodiments relate to the formation of self-aligned gate contacts utilizing the formation of self-aligned growth pillars. The pillars lead to taller gate heights and increased margins against shorting defects.

Self-aligned contact and contact over active gate structures

Methods and apparatus for inspecting features on a substrate including exposing at least a portion of the substrate to a first electron beam landing energy to obtain a first image; exposing the at least a portion of the substrate to a second electron beam landing energy to obtain a second image, wherein the second electron beam landing energy is different from the first electron beam landing energy; realigning the first image and the second image to a feature on the substrate; and determining from at least one measurement from the first image associated with the feature and at least one measurement from the second image associated with the feature if the feature is leaning or twisting.

Methods and apparatus for performing profile metrology on semiconductor structures

Apparatuses and methods to provide a fully self-aligned via are described. Some embodiments of the disclosure utilize a cap layer to protect an insulating layer in order to minimize bowing of the side walls during metal recess in a fully self-aligned via. The cap layer can be selectively removed, thus increasing the aspect ratio, by exposing the substrate to a hot phosphoric acid solution.

Growing community of inventors

Belmont, CA, United States of America

Madhur Sachan