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Freescale Semiconductor,inc.

Madhur Kashyap

Arijit Dutta

Narayanan Kannan

Pramod Sharma

A method of estimating capacitive cell load of cells in an integrated circuit (IC) design uses first maximum capacitive load values Cin calculating risk of electromigration failure in cells of the IC design. Cis saved for a cell whose risk of electromigration failure is acceptable. For a failed cell, a revised maximum capacitive load value Cis reduced as the ratio of an actual current Irelative to the electromigration current limit Iin the weakest element of the cell. A revised actual current Iis obtained as a function of transition times with C. Cis saved for the cell if Iis less than I. Otherwise the steps of calculating Cand Iare re-iterated. Cis reduced relative to Cfor the first iteration and is further reduced relative to its previous value Cfor subsequent iterations.

Capacitive cell load estimation using electromigration analysis

A method of conducting timing analysis on an integrated circuit design includes performing a first routing operation on the design to generate a first routed design that includes redundant vias, and storing the first routed design in a first design database, and performing a second routing operation on the synthesized design to generate a second routed design that does not include redundant vias, and storing the second routed design in a second design database. Then, extractions are performed on the first and second designs and delay calculations are performing on the first and second extractions files. The first and second delay calculations are compared to determine a delay difference between the first and second designs and timing analysis is performed using the delay difference.

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Noida, India

Madhur Kashyap