International Business Machines Corporation

Madhukar L Joshi

Wilbur David Pricer

Ronald R Silverman

Glenn F Guhman

Arup Bhattacharyya

Charles T Kroll

Tsu-Hsing Yeh

Hitendra N Ghosh

Paul F Landler

Richard K Mason

The present invention encompasses a semiconductor processing device having a processing chamber in which is positioned an electrolyte oxygen pump assembly and tubing for transferring an oxygen containing gas from outside the reaction chamber to within the interior of the electrolyte oxygen pump assembly and tubing for removal of the oxygen depleted gas from within the interior of the electrolyte oxygen pump assembly. In addition, the semiconductor processing tool may further have heating elements for heating a semiconductor substrate within the processing chamber independently from heating of the electrolyte.

Method of fabricating semiconductor device

Reaction chamber having in situ oxygen generation

A three mask method is provided for making a field effect transistor which includes the use of a first mask for defining first and second spaced apart diffusion regions, each having first and second ends, a second mask for defining a contact region at the first end of the first and second diffusion regions and for defining a protected region at the gate region and source and drain electrodes of the transistor, the protected region extending between the second ends of the first and second diffusion regions, and a third mask for forming a gate electrode within the protected region and contact electrodes in the contact region. The source and drain electrodes are formed between the gate electrode and the first and second diffusion regions by ion implantation techniques. The surfaces of the first and second diffusion regions between the contact electrodes and the second end of the first and second diffusions are oxidized to provide a crossover arrangement for gate electrode wiring, when desired, without requiring additional process steps.

Three mask process for making field effect transistors

A memory is produced which has a series circuit including charge storage means, an impedance and switching means and an amplifier having an input connected to the series circuit at a point between the charge storage means and the impedance and an output coupled to a bit/sense line. The switching means is controlled by a pulse from a word line. The series circuit interconnects the bit/sense line and a point of reference potential. In a preferred embodiment, the switching means is a first field effect transistor having its gate electrode connected to the word line and the amplifier is a second field effect transistor having its gate electrode connected to the series circuit at a point between the charge storage means and the impedance and having one of its current carrying electrodes coupled to the bit/sense line and its other current carrying electrode coupled to a point of reference potential.

Capacitor memory with an amplified cell signal

A method for making high density integrated circuits which utilizes lift-off techniques provides a structure having a single layer of insulating material for both the dielectric of a storage capacitor and the insulator for a gate or control electrode of a switching element. The steps of the method include forming a thin layer of silicon dioxide on a silicon substrate followed by a layer of first doped polysilicon and, optionally, a layer of silicon nitride and then a layer of photoresist. The layers are etched to the silicon dioxide surface with the exception of the portion of the layers overlying a region defined as the gate or control electrode of the switching element. A second layer of doped polysilicon is then deposited over the remaining structure to provide on the silicon dioxide layer a second conductive layer adjacent to but spaced from the first polysilicon layer forming the gate or control electrode. The silicon nitride, when used, is etched away and a strip of conductive metal is placed in contact with the first conductive polysilicon layer after the second doped polysilicon layer has been appropriately oxidized to form an insulating medium over this second polysilicon layer and between the first and second polysilicon layers. Any desired n+ regions may be formed in the silicon substrate by diffusing impurities into the substrate prior to forming the silicon dioxide layer, or the n+ regions may be formed after the silicon dioxide has been formed by using appropriate ion implantation techniques. By employing this method, high density one device memory arrays may be produced by using the first doped polysilicon layer for forming the gate electrode of a field effect transistor and the second doped polysilicon layer as an electrode of the storage capacitor.

Integrated circuit process utilizing lift-off techniques

A substantially square N-type impurity distribution profile in a silicon substrate produces much superior dc and ac characteristics in PN junction devices than can be expected from the usual phosphorus distribution profile. Such a square profile is obtained by diffusion of arsenic in the silicon substrate. The sharper impurity gradient allows a relatively low surface concentration to be used for the device. This lower surface concentration relieves precipitation and dislocation problems.

Utilization of an arsenic diffused emitter in the fabrication of a high

Fully integrated non-volatile and fixed threshold field effect devices are fabricated in N-channel technology on a single semiconductor substrate. MOSFET devices of the metal-nitride-oxide-semiconductor (MNOS) devices are used both as fixed threshold support devices and as variable threshold non-volatile memory array devices. Extremely stable and reproducible device characteristics result from the use of low charge containing dielectrics which allow optimum variable threshold stability and allow the use of operating potentials compatable with conventional fixed threshold FET devices. Low temperature processing following deposition of variable threshold gate dielectric enables all enhancement mode operation. A field oxide structure including a thin silicon dioxide layer, an aluminum oxide layer and a nitride layer provides parasitic threshold voltages in excess of 60 volts and prevents sub-threshold leakage.

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Essex Junction, VT, United States of America

Madhukar L Joshi