Fairchild Camera and Instrument Corp.

National Semiconductor Corporation

Terapede Systems Inc.

Fairchild Semiconductor Corporation

Suvolta, Inc.

Dsm Solutions, Inc.

Other

Dynalogic

Dynachip Corporation

Fairchild Camera & Instr. Corp.

Terapede, LLC

National Seimconductor Corporation

Madhukar B Vora

Ashok K Kapoor

Burnell G West

Hemraj K Hingarh

Brian Rodricks

James S Koford

Michael E Thomas

Christopher Luis Hamlin

Payman Zarkesh-Ha

William H Herndon

Andrew C Tickle

Greg Burton

Paul T Sasaki

Gregory N Burton

Werner F Rust

Vikram M Patel

C Michael Powell

Hermaj K Hingarh

Various embodiments of a 3D high resolution X-ray sensor are described. In one aspect, an indirect X-ray sensor includes a silicon wafer that includes an array of photodiodes thereon with each of the photodiodes having a contact on a front side of the silicon wafer and self-aligned with a respective grid hole of an array of grid holes that are on a back side of the silicon wafer. Each of the grid holes is filled with a scintillator configured to convert beams of X-ray into light. The indirect X-ray sensor also includes one or more silicon dies with an array of photo-sensing circuits each of which including a contact at a top surface of the one or more silicon dies. Contact on each of the photodiodes is aligned and bonded to contact of a respective photo-sensing circuit of the array of photo-sensing circuits of the one or more silicon dies.

3D high resolution X-ray sensor with integrated scintillator grid

Various embodiments of a structure implemented in an X-ray imaging system are described. In one aspect, a structure implemented in an X-ray imaging system includes a silicon wafer including a first side and a second side opposite the first side. The silicon wafer also includes an array of photodiodes on the first side of the silicon wafer with the photodiodes electrically isolated from each other as well as an array of grid holes on the second side of the silicon wafer. Each grid hole of the array of grid holes is aligned with a respective photodiode of the array of photodiodes. The structure also includes a layer of scintillating material disposed over the array of grid holes on the second side of the silicon wafer. The structure further includes a layer of reflective material disposed on the layer of scintillating material.

Integrated scintillator grid with photodiodes

An electronic circuit and method may include a first chip including first electronics and a first connector including multiple self-alignment features and conductive pads. A second chip may include second electronics and a second connector including multiple self-alignment features and conductive pads. The first chip and second chip may be indirectly horizontally aligned with one another and in electrical communication with one another via the first and second connectors.

Apparatus and methods for high-density chip connectivity

Seemless tiling and high pixel density in a 3D high resolution x-ray sensor with integrated scintillator grid for low noise and high image quality

Self-alignment structures, such as micro-balls and V-grooves, may be formed on chips made by different processes. The self-alignment structures may be aligned to mask layers within an accuracy of one-half the smallest feature size inside a chip. For example, the alignment structures can align an array of pads having a pitch of 0.6 microns, compared to a pitch of 100 microns available with today's Ball Grid Array (BGA) technology. As a result, circuits in the mated chips can communicate via the pads with the same speed or clock frequency as if in a single chip. For example, clock rates between interconnected chips can be increased from 100 MHz to 4 GHz due to low capacitance of the interconnected pads. Because high-density arrays of pads can interconnect chips, chips can be made smaller, thereby reducing cost of chips by order(s) of magnitude.

A method for modeling a circuit includes generating a circuit model based on a netlist that defines a plurality of connections between a plurality of circuit elements. The circuit model includes a model of one or more of the circuit elements. The method further includes determining a wire width associated with at least a selected connection based, at least in part, on design rules associated with the netlist. Additionally, the method includes determining a wire thickness associated with the selected connection based, at least in part, on a signal delay associated with the wire thickness. Furthermore, the method also includes routing the selected connection in the circuit model using a wire having a width substantially equal to the wire width calculated for the connection and a thickness equal to the wire thickness calculated for the connection and storing the circuit model in an electronic storage media.

System and method for routing connections with improved interconnect thickness

A semiconductor device can include at least a first diffusion region formed by doping a semiconductor substrate and at least a second diffusion region formed by doping the semiconductor substrate that is separated from the first diffusion region by an isolation region. At least a first conductive line can comprise a semiconductor material formed over and in contact with the first diffusion region and the second diffusion region. A portion of the first conductive line in contact with the first diffusion region is doped to an opposite conductivity type as the first diffusion region. At least a second conductive line comprising a semiconductor material is formed in parallel with the first conductive line and over and in contact with the first diffusion region and the second diffusion region. A portion of the second conductive line can be in contact with the first diffusion region and doped to a same conductivity type as the first diffusion region. A portion of the second conductive line in contact with the second diffusion region can be doped to a same conductivity type as the second diffusion region.

Semiconductor device, design method and structure

Methods and apparatus for high-density chip connectivity

A JFET structure with self-aligned metal source, drain and gate contacts with very low resistivity and very small feature sizes. Small source, drain and gate openings are etched in a thin dielectric layer which has a thickness set according to the desired source, gate and drain opening sizes, said dielectric layer having a nitride top layer. Metal is deposited on top of said dielectric layer to fill said openings and the metal is polished back to the top of the dielectric layer to achieve thin source, drain and gate contacts. Some embodiments include an anti-leakage poly-silicon layer lining the contact holes and all embodiments where spiking may occur include a barrier metal layer.

Method of forming an oxide isolated metal silicon-gate JFET

Growing community of inventors

Los Gatos, CA, United States of America

Madhukar B Vora