Qualcomm Incorporated

Madhu Yashwanth Boenapalli

Surendra Paravada

Sai Praneeth Sreeram

Venu Madhav Mokkapati

Vinod Kumar Kuruma

Ravindranath Doddi

Sravani Devineni

Hyunsuk Shin

Santhosh Reddy Akavaram

Prakhar Srivastava

Yogananda Rao Chillariga

Uday Kumar Arava

Sonali Jabreva

Sridhar Anumala

Rajendra Varma Pusapati

Sai Naresh Gajapaka

Vamsi Krishna Sambangi

Venkatesha M Iyengar

Bipul Tarafdar

Bharani Bhuvanagiri

Kaustub Naidu Paila Ram

Rajesh Kumar Biswal

Manmeet Singh Ahluwalia

Gurudutt Narasimha

Dhananjayan Athiyappan

Nishanth Kumar

Various embodiments include methods implemented in a processor for management of cryptographic keys of an integrated cryptographic engine. Embodiments may include detecting a cryptographic key access control event, determining whether the cryptographic key access control event is for disabling cryptographic key access at a cryptographic key memory of the integrated cryptographic engine, disabling cryptographic key access at the cryptographic key memory in response to determining that the cryptographic key access control event is for disabling cryptographic key access at the cryptographic key memory, and maintaining one or more cryptographic keys at the cryptographic key memory for which cryptographic key access is disabled. Embodiments may further include enabling cryptographic key access at the cryptographic key memory in response to determining that the cryptographic key access control event is not for disabling cryptographic key access at the cryptographic key memory.

Approach to protect hardware managed integrated cryptographic engine keys efficiently while preventing data at rest attacks

Methods that may be performed by a host controller of a computing device for host performance booster (HPB) mode management. Embodiments may include enabling an HPB mode based on availability of the host controller and availability of a memory device controller. In some embodiments, enabling the HPB mode based on the availability of the host controller and the availability of the memory device controller may include enabling a device control mode in response to an operating state of the host controller being busy and an operating state of the memory device controller being available. In some embodiments, enabling the HPB mode based on the availability of the host controller and the availability of the memory device controller may include enabling a host control mode in response to the operating state of the host controller being available and the operating state of the memory device controller being busy.

Efficient offloading of background operations

A Peripheral Component Interconnect Express (PCIe) system and method achieve reduced latency and improved performance by reconfiguring the PCIe link to use an increased number of lanes for retransmitting data packets held in a replay buffer if one or more data packets transmitted by the TX device are flagged as not acknowledged (NACK) by the RX device. Before retransmitting the NACK-flagged packet(s), the link is reconfigured to use a greater number of lanes, preferably the maximum number of lanes that are available for use, and then the NACK-flagged packet(s) is retransmitted using the greater number of lanes until successful receipt of the NACK-flagged packets has been acknowledged by the RX device. Once the NACK-flagged packet(s) is successfully received by the RX device, the link is reconfigured to use the previous number of lanes and operations of the link resume using the previous number of lanes.

Systems and methods for reducing latency and improving performance in a peripheral component interconnect express (PCIe) system

A Peripheral Component Interconnect Express (PCIe) system and method achieve reduced power consumption and latency. When the link transitions from an active functional state in which the link has a first configuration of N active lanes to a power-saving state, the number of active lanes is collapsed such that M of the N lanes are maintained in an active power-saving state and P of the N lanes are maintained in an electrically idle state, where M, N and P are positive integers and N>P>M. The reduction in lane width reduces power consumption. Bit values specifying the current link configuration can be saved in a control register and read and compared to bit values contained in a link control register before transitioning back to the active functional state. If the bit values match, the active functional state is resumed directly from the recovery state, thereby reducing latency.

Systems and methods for reducing latency and power consumption in a peripheral component interconnect express (PCIe) system

A host device includes a memory configured to store a logical-to-physical address mapping table of a flash memory device. The host device also includes one or more processors coupled to the memory and configured to be coupled to the flash memory device. The one or more processors are configured to determine whether a trigger condition is satisfied. The trigger condition is associated with checking a distribution of write data that is written to the flash memory device. The one or more processors are also configured to, based on a determination that the trigger condition is satisfied, identify a die of the flash memory device that has a higher data occupancy than at least one other die of the flash memory device, and send a command to the flash memory device to move data from the identified die to one or more other dies of the flash memory device.

Write throughput improvement of flash memory device

This disclosure provides systems, methods, and devices for memory systems that support packed commands for improved performance and reduced power consumption. In a first aspect, a method of accessing data in a flash memory system includes a host memory controller receiving a plurality of commands from a storage driver for execution by a flash memory device; packaging, by the memory controller of the host device, the plurality of commands as a packed command in a packet; and transmitting, by the memory controller of the host device to the flash memory device, the packet comprising the packed command for execution by the flash memory device. The use of packed commands may be based on determining the command acknowledgement delay from the flash memory device exceeds a threshold delay. Other aspects and features are also claimed and described.

Packed commands for communicating with flash memory system

A Peripheral Component Interconnect Express (PCIe) system is configured to determine when the frequency of link speed switching needed to service incoming and upcoming client requests is too high. The system is also configured to determine a modest link speed to be used to service incoming and upcoming client requests in cases where the link speed switching that will be needed is too high and causes the incoming and upcoming client requests to be serviced at the modest link speed instead of at the link speeds associated with the predefined BWs of the clients. By doing this when the frequency of link speed switching needed is too high, the PCIe system achieves better throughput while also reducing power consumption.

Systems and methods for performing link speed switching in a peripheral component interconnect express (PCIe) system

This disclosure provides systems, methods, and devices for memory systems that support enhanced write buffer flush schemes. In a first aspect, a method performed by a memory controller includes maintaining a list of data segments stored in a write buffer having a single-level cell memory architecture. The list includes, for each entry of the list, a data segment identifier of a respective data segment and an available contiguous memory space in the write buffer if the data segment is flushed. The list is sorted based on the available contiguous memory space. The method includes detecting a flush opportunity and initiating, based on the detecting, a flush operation to write a first data segment that corresponds to a first entry of the list from the write buffer to a memory module having a higher storage density memory architecture. Other aspects and features are also claimed and described.

Enhanced write buffer flush scheme for memory devices with high density storage memory architecture

This disclosure provides systems, methods, and devices for memory systems that support enhanced write buffer flush schemes. In a first aspect, a method performed by a memory controller includes detecting, by the memory controller, a flush operation associated with a write buffer. The method also includes detecting, by the memory controller during the flush operation, a command for placement into a command queue. The method further include prioritizing, by the memory controller, the flush operation to by placing the command in a wait queue and maintaining the flush operation. Other aspects and features are also claimed and described.

Aspects of the present disclosure provide various techniques, apparatuses, and methods that can improve the write throughout of a data storage device. In some aspects, the storage device can be provided with multiple write buffers to improve write throughput. In some aspects, the data storage device can continue to handle commands using a command queue while performing a write buffer flush operation. Therefore, the data storage device can avoid suspending the write buffer flush operation when a new command is received by the command queue. In some aspects, the storage device can perform a write buffer flush operation when a command queue is not empty.

Memory devices write buffer management

Methods that may be performed by a universal flash storage (UFS) system of a computing device for updating logical-to-physical (L2P) address mapping tables. Various embodiments may include enabling a device control mode (DCM) of host performance booster (HPB) based on a flush of a writebooster buffer to a normal storage of a UFS device of the UFS system, and updating an L2P address mapping table at a host device of the UFS system while DCM is enabled based on the flush of the writebooster buffer to the normal storage. Some embodiments may include generating a signal having an indicator of a UFS protocol information unit configured to indicate a change in an HPB mode at the UFS device based on the flush of the writebooster buffer to the normal storage, and sending the signal from the UFS device to the host device.

Universal flash storage read throughput enhancements

Methods that may be performed by a host controller of a computing device for synchronizing logical-to-physical (L2P) tables before entering a hibernate mode are disclosed. Embodiment methods may include determining whether a first L2P table stored in a dynamic random-access memory (DRAM) communicatively connected to the host controller is out of synchronization with a second L2P table stored in a static random-access memory (SRAM) of a universal flash storage (UFS) device communicatively connected to the host controller via a link. If the first and second L2P tables are out of synch, the host controller may retrieve at least one modified L2P map entry from the second L2P table when the UFS device is configured to enter a hibernate mode from the UFS device, and update the first L2P tabled with the at least one modified L2P map entry before the link and the UFS device enter the hibernate mode.

Host performance booster L2P handoff

A method may involve receiving fingerprint sensor data from a fingerprint sensor system, detecting, according to the fingerprint sensor data, a presence of a digit on an outer surface of the apparatus in a fingerprint sensor system area; determining, according to the fingerprint sensor data, a digit force or a digit pressure of the digit on the outer surface of the apparatus; and making, according to the fingerprint sensor data, a time threshold determination. The time threshold determination may involve determining whether a length of time during which the digit force exceeds a threshold digit force or during which the digit pressure exceeds a threshold digit pressure is greater than or equal to a threshold length of time. The method may involve determining, based at least in part on the time threshold determination, whether to enable one or more emergency response functions of the apparatus.

Emergency or stealth responses triggered by fingerprint sensor

Systems and methods for fast memory access are disclosed. In one aspect, a processor such as, for example, a control circuit in a system on a chip (SoC) that couples to an external memory such as, for example a Universal File System (UFS) memory (e.g., a NAND flash memory) with a partial logical to physical (L2P) mapping table stored in the external memory as well as a local L2P mapping table stored in a local memory (e.g., dynamic random-access memory (DRAM)). The control circuit may evaluate what percentage of entries in the local L2P mapping table are active compared to inactive. If the number of inactive exceeds the number of active, the control circuit may send a read command without accessing the local L2P mapping table.

Systems and methods for fast memory access

A method of shuffling turbo-write buffers of a universal flash storage system is described. The method includes periodically determining a performance index of each turbo-write buffer allocated to a unique logical unit number of the universal flash storage system. The method also includes shifting a position of at least two of the turbo-write buffers according to the performance index of each of the turbo-write buffers and a threshold performance level.

Growing community of inventors

Hyderabad Telangana, India

Madhu Yashwanth Boenapalli