Brocade Communications Systems, Inc.

Avago Technologies International Sales Pte. Limited

Madhsudan Hans

Kung-Ling Ko

Pashupati Kumar

Vidyasagara Reddy Guntaka

Amr Sabaa

Bao Vu

Poulo Kuriakose

Tarak Parekh

Systems for performing inline wire speed data deduplication are described herein. Some embodiments include a device for inline data deduplication that includes one or more input ports for receiving an input data stream containing duplicates, one or more output ports for providing a data deduplicated output data stream, and an inline data deduplication engine coupled to said one or more input ports and said one or more output ports to process input data containing duplicates into output data which is data deduplicated, said inline data deduplication engine having an inline data deduplication bandwidth of at least 4 Gigabytes per second.

Inline wire speed deduplication system

Systems for performing inline wire speed data deduplication are described herein. Some embodiments include a device for inline data deduplication that includes one or more input ports for receiving an input data stream containing duplicates, one or more output ports for providing a data deduplicated output data stream, and an inline data deduplication engine coupled to one or more input ports and one or more output ports to process input data containing duplicates into output data which is data deduplicated, where the inline data deduplication engine has an inline data deduplication bandwidth of at least 4 Gigabytes per second.

Systems for hardware-accelerated lossless data compression are described. At least some embodiments include data compression apparatus that includes a plurality of hash memories each associated with a different lane of a plurality of lanes (each lane including data bytes of a data unit being received by the compression apparatus), an array including array elements each including a plurality of validity bits (each validity bit within an array element corresponding to a different lane of the plurality of lanes), control logic that initiates a read of a hash memory entry if a corresponding validity bit indicates that said entry is valid, and an encoder that compresses at least the data bytes for the lane associated with the hash memory comprising the valid entry if said valid entry comprises data that matches the lane data bytes.

Hardware-accelerated lossless data compression

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San Ramon, CA, United States of America

Madhsudan Hans