Georgia Tech Research Corporation

International Business Machines Corporation

Avx Corporation

E. I. Du Pont De Nemours

E-System Design, Inc.

Madhavan Swaminathan

George E White

Sidharth Dalmia

Venkatesh V Sundaram

Gordon J Robbins

Michael F McAllister

Keshav B Prasad

Eric D Perfecto

Chandrika Prasad

James A McDonald

Ege Engin

Vinu Govind

Jinwoo Choi

Gregory Martine Wilkins

Prathap Muthana

Ki Jin Han

Laertis Economikos

Thomas Anthony Wassick

Mukta S Farooq

Lixi Wan

Krishna Srinivasan

Amit Bavisi

Venkatesh Sundraram

Tae Hong Kim

Krishna Bharath

Bruce Kim

Abijit Chatterjee

Jae Young Choi

Jianyong Xie

David Chong Zhang

Power supply rejection (PSR) peaking in Low Dropout (LDO) voltage regulators can lead to reduced bandwidth and efficiency. The present invention is directed to a new design method by combining power transmission lines (PTL) with LDOs for enhancing its bandwidth and efficiency. This approach is applicable for LDOs regulating high speed I/O drivers. The PTL combined with decoupling capacitors on the package or board are used to mitigate the PSR peaking. This methodology is demonstrated using printed circuit board test vehicles with off-the-shelf components. When compared to conventional approaches, the PTL solution showed &#x2dc;80% lower power supply noise.

System and method for enhancing bandwidth of low-dropout regulators using power transmission lines for high speed input output drivers

In a method for modeling electromagnetic effects in a planar circuit that employs a plurality of through-silicon vias in a domain, a region around each through-silicon via is described in terms of a cylindrical accumulation mode basis function. The cylindrical accumulation mode basis function is incorporated into an equivalent circuit that describes selected electrical characteristics of each through-silicon via. A plurality of localized intervals around each through-silicon via is selected. A multilayer Green's function is approximated for I(wherein M and N identify selected layers and wherein zz' designates layer boundaries in a layer through which the through-silicon via passes) in each localized interval without approximating the Green's function over the entire domain. Coefficients Iare approximated over a predetermined range of frequencies (&#x3c9;). Admittance parameters based on of Iare calculated over a frequency sweep.

Modeling TSV interposer considering depletion capacitance and substrate effects

In a method for simulating temperature and electrical characteristics within an circuit, a temperature of at least one volume within the circuit as a function of a resistance within the at least one volume is repeatedly calculated and the resistance as a function of the temperature is repeatedly calculated until the temperature is within a predetermined tolerance of a previous temperature result and until the resistance is within a predetermined tolerance of a previous resistance result. Once the temperature is within a predetermined tolerance of the previous temperature result and the resistance is within a predetermined tolerance of the previous resistance, then an output indicative of the temperature is generated.

Electrical-thermal co-simulation with joule heating and convection effects for 3D systems

In a method of simulating electrical characteristics of a circuit board having a plurality of features, the plurality of features is projected onto a planar construct. A Delaunay triangulation routine for generating a triangular mesh that corresponds to the single planar construct is executed on the digital computer. A routine that generates a Voronoi diagram corresponding to the triangular mesh. An equivalent circuit for each triangle is determined. The equivalent circuit includes exactly three sub-circuits that couple a vertex within the triangle to a vertex within an adjacent triangle and exactly one sub-circuit that couples the vertex within the triangle to a reference plane. A routine solves, for each triangle, an equation describing an electrical characteristic value based on the equivalent circuit corresponding to the triangle. A routine for generating a human-perceptible indication of the electrical characteristic value for each triangle is executed on the digital computer.

Modeling of multi-layered power/ground planes using triangle elements

Disclosed are apparatus, methods and software that implement a partial element equivalent circuit (PEEC) method having global basis functions on cylindrical coordinates to determine wide-band resistance, inductance, capacitance, and conductance from a large number of three-dimensional interconnections in order to provide for the electrical design of system-in-package (SIP) modules, and the like. The apparatus, methods and software use a modal equivalent network from mixed potential integral equation with cylindrical conduction and accumulation mode basis functions, which reduces the matrix size for large three-dimensional interconnection problems. Combined with these modal basis functions, the mixed potential integral equations describe arbitrary skin and proximity effects, and allow determination of partial impedance and admittance values. Additional enhancement schemes further reduces the cost for computing the partial inductances. Therefore, the apparatus, methods and software can be used to construct accurate models of a large number of three-dimensional interconnection structures, including more than 100 bonding wires used for stacking integrated circuit chips, through-silicon via interconnections, and the like.

Modeling electrical interconnections in three-dimensional structures

Organic laminate stack ups are disclosed for a variety of applications, including high frequency RF applications. One or more inner core layers may be disposed between outer layers along with bondply or prepreg layers as needed. Discrete devices, including surface mount components and flip chips, may be embedded within the organic laminate stack up structures. The embedding of the discrete devices, which may be active or passive devices, may be in the form of a layer of bondply or prepreg encapsulating the discrete devices. In addition or in the alternative, cavities may be formed in at least the outer layers for housing discrete devices, which include surface mount components, flip chips, and wire bonded integrated circuits. A variety of caps may be utilized to seal the cavities. Further, shielding may be provided for the organic laminate stack up structure, including through a wall of vias or a plated trench cut along at least one side of the stack up structure. Each stack up structure may be packaged in a variety of ways, including as a surface mount component, ball grid array, or land grid array.

Heterogeneous organic laminate stack ups for high frequency applications

In a method for simulating electrical characteristics of a plurality of power planes, each power plane includes a plurality of geometric features. The geometric features of each power plane are projected onto a single planar construct. A polygonal mesh, including a plurality of pairs of interconnected nodes, that corresponds to the single planar construct is generated. The polygonal mesh is projected onto at least one power plane an equivalent circuit between each adjacent node of the plurality of interconnected nodes is projected onto the power plane. An equivalent capacitance is assigned between each node and a common ground planer. A finite element equation that includes a plurality of discrete terms is generated. The equation is solved, thereby determining the electrical characteristic value between each pair of adjacent nodes.

Multi-layer finite element method for modeling of package power and ground planes

The present invention describes methods and apparatus for electromagnetic band gap structure synthesis. An exemplary embodiment of the present invention provides a method of electromagnetic band gap structure synthesis, which includes the step of providing a set of desired characteristics for an electromagnetic band gap structure. Furthermore, the method includes generating populations of patch shape members with a genetic algorithm routine and solving one or more of patch shape members of the populations with an electrodynamics modeling technique. Thereafter, the method includes the step of converting the output of the electrodynamics modeling technique into a set of response data for one or more of the patch shape members and calculating a fitness level for one or more of the sets of response data in comparison to the set of desired characteristics for the electromagnetic band gap structure. Next, the method includes the step of determining whether the fitness level of one of the patch shape members is within a predetermined tolerance. Subsequently, if none of the patch shape members provides a fitness level within the predetermined tolerance, then the steps of generating, solving, converting, calculating, and determining are repeated.

Systems and methods for electromagnetic band gap structure synthesis

The present invention provides all organic fully-packaged miniature bandpass filters, baluns, diplexers, multiplexers, couplers and a combination of the above manufactured using liquid crystalline polymer (LCP) and other multilayer polymer based substrates. These devices are manufactured using one or more LCP layers having integrated passive components formed thereon to provide the density and performance necessary for multi-band wireless devices. In the designs involving multiple LCP layers, the LCP layers are separated by prepeg layers. In accordance with an aspect of the present invention, coplanar waveguide, hybrid stripline/coplanar waveguide and/or microstrip topologies are utilized to form the integrated passive components, and the devices can be mass produced on large area panels at least 18 inches by 12 inches with line widths smaller than 10 um.

Liquid crystalline polymer and multilayer polymer-based passive signal processing components for RF/wireless multi-band applications

Disclosed are exemplary finite difference methods for electromagnetically simulating planar multilayer structures. The exemplary finite difference methods simulate multilayer planes by combining the admittance matrices of single plane pairs and equivalent circuit models for such single plane pairs based on multilayer finite difference approximation. Based on the methods, coupling between different layers through electrically large apertures can be modeled very accurately and efficiently.

Multilayer finite difference methods for electrical modeling of packages and printed circuit boards

The present invention includes methods for making liquid crystalline polymer (LCP) interconnect structures using a high temperature and low temperature single sided LCP, where both the high and low temperature LCP are provided with a z-axis connection. The single sided conductive layer is a bus layer to form z-axis conductive stud within the high and low temperature LCP. High and low temperature LCP layers are etched or built up to form circuit patterns and subsequently bonded together to form final multilayer circuit pattern where the low temperature LCP melts to form both dielectric to dielectric bond to high temperature LCP circuit layer, and dielectric to conductive bond.

Method for fabricating three-dimensional all organic interconnect structures

One embodiment of the present invention provides advice for providing a low noise power supply package to an integrated circuit comprising a semiconductor die, input/output power supply terminals, and an array of embedded ceramic capacitors selected from discrete, planar and combinations thereof wherein said capacitors are placed in the locations selected from within the perimeter of the shadow of the semiconductor die, partially within the perimeter of the shadow of the semiconductor die, near the perimeter of the shadow of the semiconductor die, and combinations thereof.

Device having an array of embedded capacitors for power delivery and decoupling of high speed input/output circuitry of an integrated circuit

One embodiment of the present invention provides a device for providing a low noise power supply package to an IC in the mid-frequency range of 1 MHz to 3 GHz including installing in said package an array of embedded discrete ceramic capacitors, and optionally planar capacitor layers. A further embodiment provides a device for providing a low noise power supply package to an IC in the mid-frequency range of 1 MHz to 3 GHz including an array of embedded discrete ceramic capacitors with different resonance frequencies, arranged in such a way that the capacitor array's impedance vs frequency curve in the critical mid-frequency range yields impedance values at or below a targeted impedance value.

Packaging having an array of embedded capacitors for power delivery and decoupling in the mid-frequency range and methods of forming thereof

The present invention allows for the use of chip-package co-design of RF transceivers and their components by using discrete active devices in conjunction with passive components. Two particular components are described, including voltage controlled oscillators (VCOs) and low noise amplifiers (LNAs). The high quality passive components for use in the VCOs and LNAs may be obtained by the use of embedded passives in organic substrates. Further, the embedded passives may have multi-band characteristics, thereby allowing multi-band VCOs and LNAs to be implemented with fewer components. In situations where size is a concern, the active devices and passive components utilized in an RF transceiver may be implemented in a low form factor module of less than 1.1 mm thick according to an embodiment of the invention.

Growing community of inventors

Marietta, GA, United States of America

Madhavan Swaminathan