International Business Machines Corporation

Kabushiki Kaisha Toshiba

Mack Wayne Riley

Nathan Paul Chelstrom

Michael Fan Wang

David William Boerstler

Eskinder Hailu

Michael Wayne Harper

Ingemar Holm

Stephen Douglas Weitzel

Matthew E Fernsler

Ralph C Koester

Kirk David Peterson

William Paul Hovis

Tilman Gloekler

Nathaniel R Chadwick

Steven Ross Ferguson

Irene Beattie

Frances S M Clougherty

Jieming Qi

Daniel Lawrence Stasiak

Sang Hoo Dhong

Charles Ray Johns

Cedric Lichtenau

Brian King Flachs

Thomas Pflueger

Brad William Michael

John Samuel Liberty

Larry Scott Leitner

Gilles Gervais

Naoki Kiryu

Michael B Spear

John Daniel Upton

Parag Birmiwal

David W Shan

John G Rell, Iii

Cindy Phan

Polisetty V N Srinivas

Shoji Sawamura

Ra'ed M Al-omari

Devi Shanmugam

Method and apparatus for packeted analysis, comprising: testing a phase rotator at a plurality of phase rotator positions, by propagating a first series of bits of a first pattern through a channel of an integrated circuit; propagating a second series of bits of a second pattern through the channel; measuring, for the given phase rotator position, a value of each bit propagated through the channel; and in response to determining that measured values of the bits propagated through the channel conform to one of the first pattern and the second pattern, indicating that the given phase rotator position satisfies an accuracy threshold; determining a sequence of phase rotator positions of the plurality of phase rotator positions in which the accuracy threshold is satisfied; and in response to determining that the sequence of phase rotator positions does not satisfy an eye width threshold, failing the channel of the integrated circuit.

Built-in self-test for receiver channel

An electronic system is disclosed, which may include a phase pipeline, a data pipeline, an input phase selector, and an output phase selector. The phase pipeline may have latches clocked by a clock signal, and designed to propagate phase signals from a phase input to a phase output. The data pipeline may have latches clocked by the phase pipeline clock signal, and designed to propagate data from a data input to a data output. The input phase selector may be designed to provide an inverted or a non-inverted copy of data from a data input, in response to a value at the phase input, to the data pipeline data input. The output phase selector may be designed to provide an inverted or a non-inverted copy of data from the data pipeline output to an output phase selector data output, in response to a phase pipeline output value.

Circuit design for balanced logic stress

Provided is an apparatus that includes a processor comprising a plurality of processing cores and a corresponding plurality of LBIST modules, each LBIST module corresponding to one of the plurality of processing cores; a MISR read out connection, comprising a compare value register, a plurality of MISR registers equal in number to the plurality of cores, each MISR register corresponding to one of the plurality of processing cores and a corresponding plurality of XOR logic gates, each XOR logic gate coupled to the compare value register and a corresponding one of the MISR registers and configured to signal whether or not the event the compare value register and the corresponding MISR register match and logic, stored and executed on the processor, for transmitting the signals generated by the plurality of XOR logic gates.

Evaluation of multiple input signature register results

An integrated circuit includes an LBIST controller operative to run a test program on at least one selection of core logic of the integrated circuit to test the operability of the at least one selection of core logic. The integrated circuit also includes a monitoring logic structure operative to detect at least one type of operation executed for the test program from at least one particular control signal activated by the LBIST controller for controlling the at least one selection of core logic to execute the test program from among at least one control signal for controlling operations on the at least one selection of core logic.

On-chip detection of types of operations tested by an LBIST

A mechanism is provided for identifying a failing latch within an integrated circuit device. A test sequence is initiated on a set of scan chains associated with an identified failing multiple input signature register. For each test portion in a set of test portions in the test sequence, a comparison is performed between an output of the multiple input signature register and a corresponding value in a set of expected values. Responsive to determining a match, a value of a counter is incremented. Responsive to a failure to match, incrementing of the counter is stopped, and the value of the counter providing an indication of the failing latch in the integrated circuit device is read out.

Isolating failing latches using a logic built-in self-test

Various embodiments include approaches for determining burn-in workload conditions for an integrated circuit (IC) design. Some embodiments include burn-in testing the IC design using the workload conditions. In some embodiments, a computer implemented method includes obtaining survey data about at least one application workload for an integrated circuit (IC) corresponding to an IC design; generating latch state and clocking statistics about the IC design for the at least one application workload based upon the survey data; and determining a set of burn-in workload conditions for the IC design based upon the latch state and clocking statistics about the IC design.

Determining chip burn-in workload using emulated application condition

Provided is a method for the collection and storage of information related to the operation of a chip module. The disclosed technology provides a chip data collection and storage controller. In one embodiment, a chip module is provided with a stand-alone memory that records information relevant to potential debugging operations. The stand-alone memory is on the same chip module as the chip die but is not part of the chip die. A data bus is provided between the chip module and the memory. In addition, the memory has I/O access so that information can be accessed in the event that the chip module cannot be accessed. Stored information includes, but is not limited to, environmental conditions, performance information, errors, time usage, run time, number of power on cycles, the highest temperature experience by the chip, wafer and x, y data, manufacturing info, FIR errors, and PRSO, SRAM PSRO values.

Information collection and storage for single core chips to 'N core chips

A mechanism for controlling asynchronous clock domains to perform synchronous operations is provided. With the mechanism, when a synchronous operation is to be performed on a chip, the latches of the functional elements of the chip are controlled by a synchronous clock so that the latches are controlled synchronously even across asynchronous boundaries of the chip. The synchronous operation may then be performed and the chip's functional elements returned to being controlled by a local clock in an asynchronous manner after completion of the synchronous operation. This synchronous operation may be, for example, a power on reset (POR) operation, a manufacturing test sequence, debug operation, or the like.

Controlling asynchronous clock domains to perform synchronous operations

A method and apparatus are provided for calibrating digital thermal sensors. A processor chip with a plurality of digital thermal sensors receives an analog voltage. A test circuit coupled to the processor chip receives a clock signal and a register coupled to the test circuit outputs a value on each clock cycle to a digital thermal sensor in the plurality of digital thermal sensors. The digital thermal sensor transitions an output state in response to the value of the register received in the digital thermal sensor equaling a temperature threshold of the digital thermal sensor. The value of the register at the point of transition is used to calibrate the digital thermal sensor. An incrementer increments the value of the register on each clock cycle in response to the value of the register received in the digital thermal sensor failing to equal the temperature threshold of the digital thermal sensor.

Digital thermal sensor test implementation without using main core voltage supply

Mechanisms for testing functional boundary logic at an asynchronous clock boundary of an integrated circuit device are provided. With these mechanisms, each clock domain has its own scan paths that do not cross domain boundaries. By eliminating the scanning across the boundaries, the requirement to have two clock grids in the asynchronously clocked domains may be eliminated. As a result, circuit area and design time with regard to the clock distribution design are reduced. In addition, removing the second clock grid, i.e. the high speed core or system clock, in the asynchronously clocked domains removes the requirement to have a multiplexing scheme for selection of clocking signals in the asynchronous domain. In addition to the above, the system and method provide boundary built-in-self-test logic for testing the functional crossing logic of boundaries between the clock domains in a functional mode of operation.

Testing functional boundary logic at asynchronous clock boundaries of an integrated circuit device

A secure Power-on Reset (POR) engine is provided, inside a processor chip, which guarantees a secure initialization of the chip to enable secure code execution. External access to chip resources is limited to a very few targeted settings that do not compromise the chip security. The POR engine comprises a small state machine that runs through a predefined sequence coded in persistent memory contained in the processor chip. The state machine initializes the chip and allows external access from an external processor to only some scan chains of the processor chip in order to configure interfaces, and the like, without compromising the chip security. The state machine also manages the encryption keys that are used to verify that the code, fetched by the processor to complete the initialization in software, is not modified by a third party.

Secure power-on reset engine

An apparatus is provided to reduce transient current swings during mode transitions. Traditionally, transient supply voltage fluctuations on a chip account for a large portion of the power supply. The number of series inductances and resistances are typically minimized, while adding large decoupling capacitances between the supply voltage and ground. However, situations may arise where reduction of series inductances and resistances cannot be accomplished. Therefore, to assist in controlling the transient current swings, reduction of clocking frequencies are performed in a controlled manner.

Circuit to reduce transient current swings during mode transitions of high frequency/high power chips

A circuit for transitioning clocking speeds, or frequencies, is provided. With this circuit, a clocking circuit providing a first clock signal at a first clock frequency is coupled to a counter. A comparator and a first divider are coupled to an output of the counter. The first divider outputs a second clock signal at a second clock frequency. A second divider is interposed between the clocking circuit and the counter. A processor is coupled to an output of the first divider.

Circuit to reduce power supply fluctuations in high frequency/high power circuits

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Austin, TX, United States of America

Mack Wayne Riley