Motorola Corporation

Shure Acquisition Holdings, Inc.

Mack Mansouri

Thomas J Kundmann

Moshe Tarrab

Eran Pisek

Daniel Stewart

Myzil Elroy Boyce

Eugen Warkentin

Steven Rossi

Richard Bontrager

An adjustable clock that may be implemented on a field-programmable gate array (FPGA). The adjustable clock may be highly accurate and stable, and may be adjustable in response to software commands. The adjustable clock may be configured to generate a clock signal that is synchronized in frequency and/or phase with a clock that is external to the FPGA, such as a Precision Time Protocol (PTP) clock. The FPGA may implement the adjustable clock with a number of elements as programmable logic, including a numerically-controlled frequency divider, a multi-tap delay line, logic configured to dynamically select, for each clock pulse, a delay of the multi-tap delay line, and a feedback loop to control the numerically-controlled frequency divider.

FPGA-based adjustable clock for audio devices

A wireless microphone system efficiently combines a pair of antennas so that radio frequency (RF) signals may be transmitted to and from multiple receivers and multiple wireless microphones. The wireless microphone system supports a general radio access technology and may comply with a Digital Enhanced Cordless Telecommunications (DECT) specification. The resource manager combines a received RF component with a first digital component via a first coaxial link to a connected receiver. The receiver also combines a transmitted RF component with a second digital component via a second coaxial link to the resource manager. The first digital component further includes synchronization and data sub-components, which are separated at the receiver.

Wireless microphone system

A format programmable hardware packetizer ( ) receives real-time raw input data ( ) from a multimedia data source ( ) via an analog to digital converter ( ) and a data encoder ( ) gated by encoder interrupts ( ). The real-time raw input data is buffered in an internal byte collector of the packetizer ( ). A main CPU interrupt ( ) is issued to the main processor ( ) when a packet boundary code is received. The packetizer ( ) formats the data according to a desired format selected on line ( ) for dump to the main memory ( ) while providing a managed, much lower level of interrupts to the main processor ( ) on the CPU interrupt line ( ). A plurality of hardware packetizers ( ) can be deployed according to alternative constructions for efficient real time packetizing in various selected formats.

Format programmable hardware packetizer

A filter co-processor within a Digital Signal Processor (DSP) takes advantage of the orthogonal nature of modulated signals during the equalization process. Since, after reception, only certain real/imaginary values of the received signal are useful for demodulation, the filter co-processor only processes those values to estimate the transmitted signal. By processing only those values useful for demodulation, the filter co-processor is able to process more information in a given amount of time, leading to increased processing when compared to the prior art.

Filter co-processor

An apparatus for use in a receiver (100) of a wireless communication system is provided. The apparatus comprises a first filter (340) having a first cutoff frequency, a second filter (350) having a second cutoff frequency, a first data bit estimator (360) coupled to the first filter (340), a second data bit estimator (361) coupled to the second filter (350), a third data bit estimator (363), and decision logic (370) dynamically selecting one of the first and second filters based on a first bit count from the first data bit estimator (360), a second bit count from the second data bit estimator (361), and a third bit count from the third data bit estimator (363).

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Wheeling, IL, United States of America

Mack Mansouri