Nvidia Corporation

Maciej Piotr Tyrlik

Shirish C Gadre

Ajay Sudarshan Tirumala

Jack H Choquette

Sean Jeffrey Treichler

Ronny Krashinsky

Andrew Robert Kerr

Alan Kaatz

Rishkul Kulkarni

Apoorv Parle

Girish Bharambe

Kyrylo Perelygin

Harold Carter Edwards

Frank Joseph Eaton

Konstantinos Kyriakopoulos

Gokul Ramaswamy Hirisave Chandra Shekhara

Edward H Gornish

Aditya Avinash Atluri

Balaji Krishna Yugandhar Atukuri

Bageshri Sathe

David Allan Berson

Haicheng Wu

Vijay Thakkar

Cody Addison

Aman Arora

James Player

Cris Cecka

Daniel Alan Stiffler

Apparatuses, systems, and techniques to perform computational operations in response to one or more compute uniform device architecture (CUDA) programs. In at least one embodiment, one or more computational operations are to cause one or more other computational operations to wait until a portion of matrix multiply-accumulate (MMA) operations have been performed.

Application programming interface to wait on matrix multiply-accumulate

Various techniques for accelerating dynamic programming algorithms are provided. For example, a fused addition and comparison instruction, a three-operand comparison instruction, and a two-operand comparison instruction are used to accelerate a Needleman-Wunsch algorithm that determines an optimized global alignment of subsequences over two entire sequences. In another example, the fused addition and comparison instruction is used in an innermost loop of a Floyd-Warshall algorithm to reduce the number of instructions required to determine shortest paths between pairs of vertices in a graph. In another example, a two-way single instruction multiple data (SIMD) floating point variant of the three-operand comparison instruction is used to reduce the number of instructions required to determine the median of an array of floating point values.

Implementing specialized instructions for accelerating dynamic programming algorithms

Various techniques for accelerating Smith-Waterman sequence alignments are provided. For example, threads in a group of threads are employed to use an interleaved cell layout to store relevant data in registers while computing sub-alignment data for one or more local alignment problems. In another example, specialized instructions that reduce the number of cycles required to compute each sub-alignment score are utilized. In another example, threads are employed to compute sub-alignment data for a subset of columns of one or more local alignment problems while other threads begin computing sub-alignment data based on partial result data received from the preceding threads. After computing a maximum sub-alignment score, a thread stores the maximum sub-alignment score and the corresponding position in global memory.

Techniques for storing sub-alignment data when accelerating Smith-Waterman sequence alignments

Implementing specialized instructions for accelerating Smith-Waterman sequence alignments

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Durham, NC, United States of America

Maciej Piotr Tyrlik