Nec Corporation

Ps4 Luxco S.a.r.l.

Longitude Licensing Limited

Machio Segawa

Toru Ishikawa

Hisayuki Nagamine

One semiconductor device includes nine surface micro-bumps laid out in a 3&#xd7;3 matrix on a semiconductor substrate, a transistor that contains first and second diffusion layers formed on the semiconductor substrate, and power-supply wiring laid out on the semiconductor substrate. The aforementioned first diffusion layer is connected to one of the surface micro-bumps, the second diffusion layer is connected to the power-supply wiring, and the transistor is laid out in the region between the surface micro-bumps located on one edge in an X direction and the surface micro-bumps located on the other edge in said X direction.

Semiconductor device

In a semiconductor device in which semiconductor chips having a number of signal TSVs are stacked, a huge amount of man-hours have been required to perform a continuity test for each of the signal TSVs. According to the present invention, no continuity test is performed directly on signal TSVs. Dummy bumps are arranged in addition to signal TSVs. The dummy bumps of the semiconductor chips are connected through a conduction path that can pass the dummy bumps between the semiconductor chips with one stroke when the semiconductor chips are stacked. A continuity test of the conduction path allows a bonding defect on bonded surfaces of two of the stacked semiconductor chips to be measured and detected.

Semiconductor device with aligned bumps

A semiconductor memory device having an improved digit line structure which is capable of carrying out a low-noise operation is disclosed. The semiconductor memory device has in each column a digit line pair and a sense amplifier connected to the digit line pair. Each pair of digit lines are composed of a plurality of first wirings formed of a first conductor layer and a plurality of second wirings formed of a second conductor layer isolated from the first conductor layer through an insulating layer. One of the digit lines of each digit line pair is formed by electrically connecting part of the first wiring and part of the second wiring, and the other digit line of the digit line pair is formed by electrically connecting the other part of the first wiring and the other part of the second wiring.

Semiconductor memory device having low noise bit line structure

A dynamic type semiconductor memory having an improved operation speed and operable by a small power consumption is disclosed. The memory cell includes a pair of bit lines which are divided into a plurality of sections, a plurality of first amplifiers provided for the sections, a second amplifier provided for the pair of bit lines. The first sense amplifier amplifies the signal at the relevant section and the second amplifier amplifies the signal from the first sense amplifier to drive a bus lines.

Growing community of inventors

Tokyo, Japan

Machio Segawa