Western Digital Technologies, Inc.

Sandisk Technologies Inc.

Hgst, Inc.

Contour Semiconductor, Inc.

Ovonyx Inc.

Mac D Apodaca

Daniel Robert Shepard

Luiz M Franca-Neto

James Juen Hsu

Thomas Michael Trent

Zhaoqiang Bai

Christopher John Petti

Neil Leslie Robertson

Michael Grobis

Gerardo Bertero

Michael Nicolas Albert Tran

Kurt A Rubin

Ricardo Ruiz

Lei Wan

Ailian Zhao

Toshiki Hirano

Jeffrey Scott Lille

Jordan Asher Katine

Guy Charles Wicker

Bruce David Terris

Lidu Huang

Federico Nardi

Derek Stewart

Thomas Brown

John C Read

Kuo-Wei Chang

Jenn C Chow

Lisa Ceder

Jon-Won S Lee

A two-step SET pulse may be applied to a phase change material of a phase change memory cell in which a first lower SET pulse is applied to make the phase change material dwell at 600K to incubate nuclei near the maximum nucleation rate and then a second higher SET pulse is immediately applied to make the phase change material dwell at 720K to maximize crystal growth. Moreover, the slope of the falling edge of a RESET pulse applied prior to the two-step SET pulse may be adjusted to increase the number of nuclei (e.g., formed with a steeper falling edge) to increase SET efficiency at the expense of a more stable amorphous phase (e.g., formed with a less steep falling edge) that improves data retention.

Set/reset methods for crystallization improvement in phase change memories

A phase change memory cell includes a first electrode, a second electrode located over the first electrode, a vertical pillar structure located between the first and second electrodes, the pillar structure containing a first phase change memory (PCM) material portion, a second PCM material portion and an intermediate electrode located between the first PCM material portion and the second PCM material portion, and a resistive liner containing a first segment electrically connected in parallel to the first PCM material portion between the first electrode and the intermediate electrode, and a second segment electrically connected in parallel to the second PCM material portion between the intermediate electrode and the second electrode. The first PCM material portion has a different electrical resistance than the second PCM material portion, and the first segment of the resistive liner has a different electrical resistance than the second segment of the resistive liner.

Multi-level phase change memory cells and method of making the same

A phase change memory device includes a phase change material portion located between a first electrode and a second electrode, and a crystallization template material portion located between the first electrode and the second electrode in contact with the phase change material portion. The crystallization template material portion and the phase change material portion belong to a same crystal system and have matching lattice spacing, or the crystallization template material portion and the phase change material portion do not belong to the same crystal system, but have a matching translational symmetry along at least one paired lattice plane with a matching lattice spacing.

Phase change memory device with crystallization template and method of making the same

Systems and methods for improving the crystallization of a phase change material of a phase change memory cell are described. A two-step SET pulse may be applied to the phase change material in which a first lower SET pulse is applied to make the phase change material dwell at 600K to incubate nuclei near the maximum nucleation rate and then a second higher SET pulse is immediately applied to make the phase change material dwell at 720K to maximize crystal growth. Moreover, the slope of the falling edge of a RESET pulse applied prior to the two-step SET pulse may be adjusted to increase the number of nuclei (e.g., formed with a steeper falling edge) to increase SET efficiency at the expense of a more stable amorphous phase (e.g., formed with a less steep falling edge) that improves data retention.

The present disclosure generally relates to semiconductor manufactured memory devices and methods of manufacture thereof. More specifically, methods for forming a plurality of layers of a 3D cross-point memory array without the need for lithographic patterning at each layer are disclosed. The method includes depositing a patterned hard mask with a plurality of first trenches over a plurality of layers. Each of the plurality of first trenches is etched all the way through the plurality of layers. Then the hard mask is patterned with a plurality of second trenches, which runs orthogonal to the plurality of first trenches. Selective undercut etching is then used to remove each of the plurality of layers except the orthogonal metal layers from the plurality of second trenches, resulting in a 3D cross-point array with memory material only at the intersections of the orthogonal metal layers.

3D cross-point memory manufacturing process having limited lithography steps

The present disclosure generally relates to the fabrication of metal-oxide-semiconductor (MOS) select transistors in a vertical orientation such that the transistor pair fits within the footprint of a 4Fmemory cell. The present disclosure further relates to the simultaneous fabrication of a vertical stack of transistors in which each transistor is distinct, as opposed to being serially connected in a NAND-like string. An initial stack of materials is built to include silicon layers to act as source and drain regions as well as to serve as epitaxial growth seed points. As such, the transistor disclosed may be utilized in conjunction with memory elements such as Phase Change, Resistive, or Magnetic RAM memory within array designs, among others.

Method to fabricate discrete vertical transistors

Resistive memory cells containing nanoparticles are formed between two electrodes. The nanoparticles may be embedded in a matrix or sintered together without a matrix. The memory cells may be projected memory cells or barrier modulated cells. Polymeric ligands may be used to deposit the nanoparticles over a substrate, followed by an optional removal or replacement of the polymeric ligands.

Nanoparticle-based resistive memory device and methods for manufacturing the same

A non-volatile storage apparatus is proposed that includes a plurality of serially connected non-volatile reversible resistance-switching memory cells, a plurality of word lines such that each of the memory cells is connected to a different word line, a bit line connected to a first end of the serially connected memory cells and a switch connected to a second end of the serially connected memory cells. In one embodiment, the memory cells include a reversible resistance-switching structure comprising a first material, a second material and a reversible resistance-switching interface between the first material and the second material, a channel, and means for switching current between current flowing through the channel and current flowing through the reversible resistance-switching interface in order to program and read the reversible resistance-switching interface. A process for manufacturing the memory is also disclosed.

Process for fabricating three dimensional non-volatile memory system

Non-volatile memory system with serially connected non-volatile reversible resistance-switching memory cells

A non-volatile memory device that limits the temperature excursion of a selector during operation to enhance the cycling life of the non-volatile memory device. A selector, in line with a memory element, may be degraded with repeated temperature excursions as current passes through a stack during the read/write process. The selector changes from an amorphous state to become crystalline thus reducing the life of a memory device. The memory device includes a word line, a bit line disposed perpendicular to the word line, a stack&#x2014;including a memory element, a selector, and a spacer&#x2014;disposed between the word line and bit line, and one or more insulating layers surrounding an outer surface of the stack disposed between the word line and bit line. By surrounding the selector with a high thermal conductive heat-sink material, heat is directed away from the selector helping maintain the selector's amorphous state longer.

Thermal management of selector

Apparatuses, systems, and methods are disclosed for a chip with phase change memory (PCM) and magnetoresistive random access memory (MRAM). An apparatus includes a semiconductor circuit formed over a substrate of a chip. An apparatus includes a PCM array formed over a semiconductor circuit. An apparatus includes an MRAM array formed over a semiconductor circuit.

Chip with phase change memory and magnetoresistive random access memory

Memory cell for non-volatile memory system

Systems and methods for providing a phase change memory that includes a phase change material, such as a chalcogenide material, in series with a heating element that comprises multiple thermal interfaces are described. The multiple thermal interfaces may cause the heating element to have a reduced bulk thermal conductivity or a lower heat transfer rate across the heating element without a corresponding reduction in electrical conductivity. The phase change material may comprise a germanium-antimony-tellurium compound or a chalcogenide glass. The heating element may include a plurality of conducting layers with different thermal conductivities. In some cases, the heating element may include two or more conducting layers in which the conducting layers comprise the same electrically conductive material or compound but are deposited or formed using different temperatures, carrier gas pressures, flow rates, and/or film thicknesses to create thermal interfaces between the two or more conducting layers.

Phase change memory electrode with multiple thermal interfaces

The present disclosure generally relates to a memory cell and methods for generating a pulse within the memory cell. As such, a geometric arrangement of transistors is disclosed that allows the transistor pulse signal generator circuit to precharge both sides of the memory cell and, subsequently, bring opposite sides of the memory cell quickly to different voltages. The circuit and wiring fabrication provided, when combined with a related transistor manufacturing process, yields pulse generating logic at the memory cell to enable the formation of a well-defined pulse while fitting within the 4Ffootprint of the memory cell. As such, the speed and pulse shape requirements of PCM, MRAM, other such cross-point memory technologies, sensor arrays, and/or pixel displays may take advantage of the reduced RC circuitry delays.

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San Jose, CA, United States of America

Mac D Apodaca