Nxp B.v.

U.S. Philips Corporation

Fluke Corporation

U.S. Phillips Corporation

Maarten Vertregt

Simon Minze Louwsma

Marcel J Pelgrom

Hans Paul Tuinhout

Atul Katoch

Gian Hoogzaad

Pim Theo Tuyls

Jose De Jesus Pineda De Gyvez

Evert Seevinck

Ajay Kapoor

Hans De Jong

Mathias Wagner

Sebastien Antonius Josephus Fabrie

Frans J List

Godefridus A Hurkx

Frank Zachariasse

Arjan Mels

William Rey

William J Rey

Kyoohyun Noh

Self-regulating body-biasing techniques for Process, Voltage, and Temperature (PVT) fluctuation compensation in Fully-Depleted Silicon-on-Insulator (FDSOI) semiconductors are disclosed. In an illustrative, non-limiting embodiment, an electronic device may include a logic cell having a plurality of FDSOI transistors manufactured thereon; and at least one current source coupled to a body terminal of each transistor in a subset of the FDSOI transistors, wherein the current source is configured to output a high-impedance current.

Self-regulating body-biasing techniques for process, voltage, and temperature (PVT) fluctuation compensation in fully-depleted silicon-on-insulator (FDSOI) semiconductors

An Analogue to Digital Converter (ADC) having a Gated Ring Voltage Controlled Oscillator, GRVCO, to generate a phase signal according to an input voltage; and a quantization circuit to generate a quantized phase output signal according. The GRVCO operates in either a first or second mode of operation according to a gating control signal. In the first mode of operation, the GRVCO operates in a VCO mode with gating disabled. In the second mode of operation, the GRVCO operates in a GRVCO mode wherein gating is enabled or disabled according to a gating signal.

Analogue to digital converter

The invention discloses an integrated circuit () for securely storing a codeword. The value of the codeword is dependent on the mobility (&#x3bc;A, &#x3bc;B, &#x3bc;C) of at least one transistor (TRA, TRB, TRC) of the integrated circuit. The invention further discloses a reader means (), a method for determining the value of the codeword from the integrated circuit (), and a method for altering the value of the codeword.

Secure storage of a codeword within an integrated circuit

It is described a method for providing an electronic key within an integrated circuit () including both a volatile memory () and a non-volatile memory (). The described comprises starting up the integrated circuit (), reading the logical state of predetermined data storage cells () assigned to the volatile memory (), which data storage cells () are characterized that with a plurality of start up procedures they respectively adopt the same logical state, and generating an electronic key by using the logical state of the predetermined data storage cells (). Preferably, the predetermined data storage cells () are randomly distributed within the volatile memory (). It is further described an integrated circuit () for providing an electronic key. The integrated circuit () comprises a volatile memory () comprising predetermined data storage cells (), which are characterized that with a plurality of start up procedures they respectively adopt the same logical state, and a non-volatile memory () having information stored upon regarding the predetermined data storage cells (). Thereby, the electronic key is defined by the corresponding logical states of the predetermined data storage cells ().

Security storage of electronic keys within volatile memories

The present application relates to an apparatus comprising a first transistor element, with at least three terminals, and at least one switching unit. The present application relates also to a method, computer readable medium having a computer program stored thereon and a track and hold circuit comprising the apparatus. The apparatus comprises a first transistor element with at least three terminals, wherein a first terminal is supplied with a first voltage, and wherein a second terminal is supplied with a second voltage. The apparatus comprises a first switching unit, wherein a third terminal is connected to ground potential via the first switching unit. The transistor element comprises a predefined threshold voltage. The first voltage and the second voltage are predefined alternating voltages. The transistor element is configured such that in case a differential voltage between the first predefined alternating voltage and the second predefined alternating voltage is higher than the predefined threshold voltage and the first switching unit is not conductive the third terminal is charged with the first predefined alternating voltage.

Time interleaved track and hold

A sampling circuit includes multiple sampling channels adapted to sample the signal in time-multiplexed fashion. Each sampling channel includes a respective track-and-hold circuit connected to a respective analogue to digital converter via a respective output switch. The output switch of each channel opens for a tracking time period when the track-and-hold circuit is in a tracking mode for sampling the signal, and closes for a holding time period when the track-and-hold circuit is in a holding mode for outputting the sampled signal. In an embodiment, the holding time period includes a settling time period that is at least as long as the tracking time period. The settling time period is used by the track-and-hold circuit to charge an input capacitance of the analogue to digital converter to a voltage according to the sampled signal.

Signal sampling circuit

During successive approximation analog to digital conversion a series of successive digital reference values is selected that converges towards a digital representation of an analog input signal. An analog reference signal is generated dependent on the successive digital reference values and compared to the analog input signal. The digital reference values are selected dependent on comparison results. In the selection of the digital reference values successive steps between digital reference values are each selected dependent on values of the comparator result from a plurality of preceding recursion cycles. The comparison results define a series of successively narrower ranges of digital values that contain a digital representation of the analog input signal. Use of a plurality of comparator results for selecting the steps in the digital reference values makes it possible to reduce uncertainty about whether the comparison result has settled. This in turn makes it possible to reduce the sizes of the successive ranges, which speeds up convergence.

Circuit with a successive approximation analog to digital converter

The invention relates to a resistor network () such as a resistor ladder network, comprising at least a resistor body () which is provided with at least a column () of taps () situated between a first tap and a second tap, wherein, in use, at least two taps can be connected with respective first and second sources of reference input potentials, and wherein each tap of the at least one column of taps can be used for outputting an output potential via a contact area which is connected with the concerning tap, wherein the resistor body () comprises a multiple of resistor sub-bodies (), wherein each resistor sub-body () is connected with a column () of taps (), and wherein the only electrical connections between the resistor sub-bodies () are established by electrical connections via taps () connected with the resistor sub-bodies (). Furthermore the invention relates to a method for manufacturing a resistor network () such as a resistor ladder network.

Resistor network such as a resistor ladder network and a method for manufacturing such a resistor network

A flash analog-to-digital converter comprises a resistive string powered by a reference voltage source for providing a set of equidistant reference voltages and a set of comparators for comparing the analog input signal with the reference voltages. A set of switches are arranged and controlled to perform an algorithm for mitigating the influence of mismatches between the components. The switches are arranged between the reference voltage source and the resistive string so that switches in the reference inputs to the comparators are avoided. The resistive string is preferably circular. The converter can handle differential signals.

Flash analog-to-digital converter

A method of displaying digital samples with enhanced image details on a raster display using a limited set of brightness values is provided. Digital samples are interpolated and stored as pixel information in high resolution intensity memory. An adaptive mapping process maps the high resolution intensity information to low intensity brightness information in a manner so as to maximize image details. An equal number of brightness levels from light to dark are allocated in each column along the sweep. An adaptive recombination process combines past and present brightness information in a manner that best preserves image details when the temporal behavior of the display image is changing. A raster display device is employed to display the image which is stored in the display memory as pixels arranged by row and column.

Method and apparatus for improving time variant image details on a

A structure with fine details, such as a periodic signal, is displayed on a raster display. To avoid aliasing due to an interference between the details and the columns and row pattern of the raster display each of the points representing the structure to be displayed is allocated to pixels in adjacent columns and/or rows. Allocation occurs by means of a stochastic procedure in which the probability to allocate a point to a pixel is dependent on the position of the point with respect to the pixel. Accumulated pixel-values are converted into a limited number of grey-values by means of an additional procedure that allows for fixed proportions of the pixels to have the same grey-value.

Image quality improvement on raster display

A semiconductor device with at least one programmable memory cell which includes a bipolar transistor (T.sub.1) with an emitter (11) and a collector (12) of a first conductivity type and a base (10) of a second, opposite conductivity type. The emitter (11) and collector (12) are coupled to a first supply line (100) and a second supply line (200), respectively. The base (10) is coupled to writing means (WRITE) through a control transistor (T.sub.2). Reading means (READ) are included in a current path (I) which extends between the first supply line (100) and the second supply line (200) and which includes a current path between the emitter (11) and collector (12). In a preferred embodiment, the collector (12) is in addition coupled to the second supply line (200) via a switchable load (T.sub.5).

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Eindhoven, Netherlands

Maarten Vertregt