Wind River Systems, Inc.

Intel Corporation

Maarten Koning

Andrew Gaiarsa

Thierry C Preyssler

Ned M Smith

Glen J Anderson

Rajesh Poornachandran

Igor G Muttik

Mark Y Kelly

Keith Nolan

Michael J Nolan

Gregory Burns

William C Deleeuw

John Brady

Zheng Zhang

Niall Cahill

John Gordon

Thiago Jose Macieira

Davide Carboni

Cliodhna Ni Scanaill

Ravikiran Chukka

Jakub Wenus

Kent Long

David N Wilner

Eugene Ryan

Richard Davies

Cy H Myers

John C Fogelin

Toby M Kohlenberg

Felix Burton

Raymond Richardson

Vincent Hue

Roger Keith Wiles

Anand N Sundaram

Tomas Evensen

Kevin McCombe

Mihai Dragusu

Remi Cote

Stephen Li

The Internet can be configured to provide communications to a large number of Internet-of-Things (IoT) devices. Devices can be designed to address the need for network layers, from central servers, through gateways, down to edge devices, to grow unhindered, to discover and make accessible connected resources, and to support the ability to hide and compartmentalize connected resources. Network protocols can be part of the fabric supporting human accessible services that operate regardless of location, time, or space. Innovations can include service delivery and associated infrastructure, such as hardware and software. Services may be provided in accordance with specified Quality of Service (QoS) terms. The use of IoT devices and networks can be included in a heterogeneous network of connectivity including wired and wireless technologies.

Internet of things

A device, system, and method performs an image compression. The method includes receiving raw image data of an image and identifying objects in the image as one of a foreground object or a background object. The method includes generating first foreground image data for a first foreground object. The method includes generating first metadata for a first background object. The first metadata indicates a first identity and a first descriptive parameter for the first background object. The first descriptive parameter relates to how the first background object is situated in the image. The method includes generating first background image data for the first background object. The first background image data is empty data. The method includes storing processed image data for the image comprising the first foreground image data, the first metadata, and the first background image data.

Image compression

Described herein are systems and methods for implementing a processor-local (e.g., a CPU-local) storage mechanism. An exemplary system includes a plurality of processors executing an operating system, the operating system including a processor local storage mechanism, wherein each processor accesses data unique to the processor based on the processor local storage mechanism. Each of the plurality of processors of the system may have controlled access to the resource and each of the processors is dedicated to one of a plurality of tasks of an application. The application including the plurality of tasks may be replicated using the processor local storage mechanism, wherein each of the tasks of the replicated application includes an affinity to one of the plurality of processors.

Method and system for a CPU-local storage mechanism

An electronic device includes a processing component and a task manager. The processing component is configurable for one of a single-core processing mode and a multi-core processing mode. The task manager determines a number of tasks running on the electronic device. The processor is configured to switch between either the single-core processing mode or the multi-core processing mode as a function of the number of tasks.

Optimizing task management

The exemplary embodiments described herein relate to systems and methods for operating system aware low latency handling. One embodiment relates to a non-transitory computer readable storage medium including a set of instructions executable by a processor, the set of instructions, when executed, resulting in a performance of receiving a fast interrupt request asserted by a hardware device while the processor is executing within a kernel critical section, executing a fast interrupt handler at a first priority level, raising a second priority level interrupt by the fast interrupt handler based on the fast interrupt request, wherein the second priority level interrupt invokes a kernel service and processing the second priority level interrupt once the processor has executed the kernel critical section.

System and method for operating system aware low latency interrupt handling

A system and method for receiving a request from a requester for access to a computing resource, instructing the requester to wait for access to the resource when the resource is unavailable and allowing the requester to perform other tasks while waiting, determining whether the requester is available when the resource subsequently becomes available, and granting access to the resource by the requester if the requester is available.

Method and system for implementing realtime spinlocks

A system and method for setting a first indicator indicating that interrupts are virtually locked, receiving a first interrupt at a processor of a computing device, setting a second indicator indicating the receipt of the first interrupt and recording a first timestamp based on the receipt of the first interrupt. The system and method further adapted to virtually execute a routine for the first interrupt that includes determining if the second indicator is set, record a second timestamp based on the virtual execution of the routine and determine an interrupt latency based on the first and second timestamp.

Interrupt latency measurement

Described herein are systems and methods for fast boot from non-volatile ('NV') memory. The exemplary embodiments relate to systems and methods for significant improvements in performance speed with simple implementations. One embodiment relates to a non-transitory computer readable storage medium including a set of instructions executable by a processor, the set of instructions operable to identify a page fault, determine whether the page fault occurred due to a read from a NV memory, copy a page from the NV memory to a random-access memory ('RAM') storage, and create an identity mapping for the page in the RAM storage. A further embodiment relates to a system comprising a NV memory, a random access memory, and a processor executing a set of instructions, wherein the set of instructions being operable to identify a page fault, determine whether a page fault occurred due to a read from the NV memory, copy a page from the NV memory to the RAM storage, and create an identity mapping for the page in the RAM storage.

System and method for fast boot from non-volatile memory

A protection domain system is implemented to provide protection for applications executing in a computing environment. Protection domains are allocated system resources and may contain executing tasks. The protection domain system may allow tasks to access resources in other protection domains to which attachments have been made. Attachment is transparent to the software developer. The protection domain system provides flexibility in implementing operating system services and defining protection hierarchies.

Protection domains for a computer operating system

Described is a method and system for optimizing a code layout for execution on a processor including internal and/or external cache memory. The method and system includes executing a program having a first layout, generating at least one memory access parameter for the program, the memory access parameter being based on a cache memory of a computing system on which the program is designed to run and constructing a second layout for the program as a function of the at least one memory access parameter.

Method and system for optimizing performance based on cache analysis

A system page is implemented to provide direct access to operating system data structures by user tasks. Frequently accessed data structures are located in the system page, and may be linked against during linking. The system page memory locations are mapped into user tasks as read-only memory locations, allowing read-only memory accesses during run-time. The system page reduces execution overhead without sacrificing system security.

Operating system permitting limited access to a system page

A task stack and a context pointer in a task control block (TCB) are implemented to provide more efficient context switching. Additionally, multiple routines each of which saves or restores a certain combination of volatile registers is implemented. A task can store in its task control block a routine identifier to select from the multiple routines a set of routines for saving and restoring volatile registers during context switching. On the occurrence of an event that may lead to a context switch a scheduler selects based on the routine identifier a routine that only saves registers used by the task, thereby, reducing execution overhead. The registers are saved on the task stack and a context pointer to the registers is saved in the TCB. In the event a context switch is necessary, it is not necessary to copy the registers to the TCB because the context pointer is in the TCB. A non-volatile register indicator that indicates whether non-volatile registers are used is stored in the task control block. The non-volatile registers are only saved if used, also reducing execution overhead. Furthermore, a storage area is implemented for saving task context for the task when it is interrupted during context switch in. Upon the occurrence of an interrupt the task context is saved in the storage area. If the interrupt leads to a second task which has a higher priority being made ready, the second task is switched in without first returning to switch-in the task.

Uniprocessor operating system design facilitating fast context switching

A computer system is provided comprising a core operating system and a system space having a number of memory locations. The core operating system creates a number of protection domains to partition the system space. Each of the partitions includes a partition operating system and a partition user application. Each partition operating system provides resource allocation services to the respective partition user application within the partition.

Two-level operating system architecture

Growing community of inventors

Bloomfield, Canada

Maarten Koning