Lsi Logic Corporation

Maad A Al-Dabagh

Alexander Y Tetelbaum

Prasad Subbarao

Radoslav Ratchkov

Bo Shen

Tammy T Huang

Thomas Mathews Antisseril

Anwar Ali

Benjamin Mbouombouo

Weidan Li

Duc Huynh

Ruben Molina, Jr

Lihui Cao

Hiroshi Ishikawa

David Gradin

A method and computer program product for finding timing critical nets in an integrated circuit design includes steps of: (a) receiving an integrated circuit design as input; (b) calculating an approximate delay for each net in the integrated circuit design wherein the approximate delay includes an estimate of crosstalk delay; (c) identifying timing critical nets from the calculated delay for each net in the integrated circuit design; (d) calculating a corresponding exact delay for each of the timing critical nets; (e) replacing the approximate delay calculated for each of the timing critical nets with the corresponding exact delay to generate a corrected set of net delays for the integrated circuit design; and (f) generating as output the corrected set of net delays for the integrated circuit design.

Method of finding critical nets in an integrated circuit design

A system, method and program product for designing integrated circuits. A design of an integrated circuit (IC) is analyzed to identify the longest path for each cell pair. The total path delay of each identified longest path is calculated. Net delays are calculated for each cell pair. A crosstalk overhead delay is calculated for each identified longest path using a stochastic model. The crosstalk overhead of each longest path is added to the calculated path delays. The circuit is redesigned to eliminate any path wherein the delay exceeds a maximum accepted delay. The stochastic model may be a tree-like structure derived from several completed integrated circuit designs, in particular from cell placement and wiring for each completed IC. The tree-like stochastic model corresponds crosstalk delays to technology wiring factors.

Integrated circuit design system and method for reducing and avoiding crosstalk

A system, method and program product for designing integrated circuits. A design of an integrated circuit (IC) is analyzed to identify the longest path between each pair of registers. A crosstalk overhead is calculated for each identified longest path using a stochastic model. The crosstalk overhead of each longest path is added to selected path delays as an incremental port of register set up time. Any path wherein the sum of the path delay and crosstalk overhead exceeds a maximum accepted delay, i.e., where slack is less than or equal to zero is redesigned and the IC is then, placed and wired. The stochastic model may be a tree-like structure derived from several completed integrated circuit (IC) designs, in particular from cell placement and wiring for the completed IC. The tree-like stochastic model corresponds crosstalk delays to technology wire factors.

Integrated design system and method for reducing and avoiding crosstalk

A method of designing an integrated circuit includes receiving as input a representation of a circuit design and a margin factor and scaling a parameter value in the circuit design by the margin factor to account for coupling in the circuit design. The margin factor advantageously reduces the number of iterations in the design flow and avoids the necessity of cross-talk analysis.

Integrated circuit design flow with capacitive margin

A method for estimating decoupling capacitance during an ASIC design flow is disclosed. The method includes precharacterizing a set of power grid structures to model their respective noise behaviors, and storing the respective noise behaviors as noise factors in a table. During the ASIC design flow for a current design that includes at least one of the precharacterized power grid structures, the corresponding noise factor from the table is used to calculate decoupling capacitance for the current design.

Decoupling capacitance estimation and insertion flow for ASIC designs

A multiple layer mesh design which includes a layer which provides a vertical mesh and an adjacent layer which provides a horizontal mesh which includes an open area or hole. The layer which provides the horizontal mesh (with hole) may either be above or below the vertical mesh layer, depending on the design. The vertical mesh may be full or may surround an open area or hole where the design includes both a horizontal donut mesh and a vertical donut mesh.

Donut power mesh scheme for flip chip package

A rectangular termination ring for a power distribution mesh is placed on the upper two layers of an integrated circuit and may be placed over some I/O circuitry. The strapping connecting the bonding pads to the termination ring are placed on upper levels of the integrated circuit, minimizing the via requirements and freeing space for additional circuitry. Further, the termination ring may be adapted to work in conjunction with L-shaped, as well as other power distribution meshes.

Termination ring for integrated circuit

An integrated circuit with a power and ground distribution system having a first conductive layer, a second conductive layer, and an insulating layer disposed between the first layer and the second layer. A first ring is formed in the first layer, where the first ring forms a first loop around a peripheral portion of the integrated circuit. First straps are formed in the first layer, where the first straps have connections to the first ring. First horizontal members are formed in the first layer, where the first horizontal members have connections to the first ring. Second horizontal members are formed in the first layer, where the second horizontal members do not have connections to the first ring. A second ring is formed in the second layer, where the second ring forms a second loop around the peripheral portion of the integrated circuit. The second ring is interleaved with the first ring. Second straps are formed in the second layer, where the second straps have connections to the second ring. Second vertical members are formed in the second layer, where the second vertical members have connections to the second ring. First vertical members are formed in the second layer, where the first vertical members do not have connections to the second ring. First vias form connections between the first vertical members and the first ring. Second vias form connections between the second horizontal members and the second ring. The first elements form a first subsystem such as for power, and the second elements form a second subsystem such as for ground.

Interleaved termination ring

A system, method and program for hierarchically designing integrated circuits(ICs). Potential sources of crosstalk are identified in the hierachical design and prior to and during placement and wiring while maintaining the hierachical structure. Blocks are placed and analyzed to determine if all blocks are well behaved and where necessary selectively re-organized to be well behaved. Blockages are inserted blocks to restrict top level wiring to avoid crosstalk. Orthogonal restrictions are placed on top level wiring as well as on top level wire lengths.

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Sunnyvale, CA, United States of America

Maad A Al-Dabagh