Motorola Corporation

Xerox Corporation

M Nghiem Phan

Roger L Hollstein

William R Blood, Jr

Robert D Berger

An open bond detection circuit is provided for verifying the continuity through a bonding wire connected between an external pin and a bonding pad of an integrated circuit by monitoring the potential developed across a metal conductor connected between the bonding pad and the power supply conductor. An output signal is provided having a first state upon detecting substantially zero potential difference across the metal conductor and a second state when detecting a non-zero potential difference across the metal conductor. The first state of the output signal with substantially zero potential difference reflects an open bond between the external pin and bonding pad, while the second state of the output signal with non-zero potential difference indicates the bonding wire is intact.

Open bond detector for an integrated circuit

A logic circuit having an emitter-follower output stage utilizes an active pull-down. An inverter stage generates a signal which drives the active pull-down, eliminating the need to identify a complementary signal in a complex logic implementation. A pre-biasing scheme for the active pull-down provides for fast turn on of the active pull-down device while eliminating the temperature and voltage dependency of the pre-biasing function. Power dissipation is minimized by operating the active pull-down and the pre-biasing network from a reduced power supply voltage.

ECL circuit with low voltage/fast pull-down

A high speed voltage translator is responsive to an ECL input signal for providing a TTL output signal at an output while clamping the low output voltage thereof to a predetermined value. The ECL input signal is converted to first and second complementary control signals for driving the upper and lower transistors in the output stage, respectively. The second control signal enables a third transistor, the base of which is connected via a serial diode and resistor combination to a second collector of the lower transistor in the output stage. The base-emitter junction potential of the third transistor cancels the potential across the diode whereby the collector of the lower transistor that is the output of the voltage translator is clamped at one base-emitter junction potential less the voltage across the resistor. Furthermore, the current flowing through the resistor is compensated for temperature variation whereby the low output voltage is independent of temperature. The first and second control signals enable separate charge and discharge paths for the upper and lower transistors whereby the associated propagation delays may be controlled so as to inhibit simultaneous conduction through the output stage.

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Mesa, AZ, United States of America

M Nghiem Phan