Intel Corporation

M Lawrence Dass

Krishna Seshan

Amir Roggel

Peng Cheng

David B Fraser

Kenneth D Karklin

Isaura S Gaeta

A method of testing an integrated circuit device including depositing a solder bump on a surface of a bond pad on an integrated circuit device, heat treating the solder bump, and testing the integrated circuit device by probing the solder bump.

Process for sort testing C4 bumped wafers

A method of exposing a bond pad includes: providing an integrated circuit having a bond pad, a first passivation layer overlying an area portion of the bond pad, and a second passivation layer overlying the first passivation layer; removing a portion of the second passivation layer above the area portion of the bond pad exposing an area of the first passivation layer; curing the second passivation; and etching a portion of the exposed area of the first passivation layer to expose the top surface of the bond pad. A method of coupling an integrated circuit chip to a chip package is also disclosed as is a method of probing the bond pads of an integrated circuit. A probe card is further disclosed, including a probe assembly coupled to a printed circuit board, the probe assembly having a sloped sidewall portion with a plurality of probing beams extending from the sidewall portion.

KLXX technology with integrated passivation process, probe geometry and

An integrated circuit passivation layer including a first passivation layer portion of silicon nitride treated with nitrous oxide and a second passivation layer portion of polyimide. Also, a method of passivating an integrated circuit wafer including depositing a first passivation layer over the top surface of an integrated circuit wafer having a scribe street area between adjacent integrated circuit device portions, depositing a second passivation layer over the first passivation layer, and patterning the first passivation layer and the second passivation layer to expose the scribe street area.

Passivation technology combining improved adhesion in passivation and a

A process for the formation of a planar epitaxial cobalt silicide and for the formation of shallow conformal junctions for use in semiconductor processing. A cobalt silicide and titanium nitride bilayer is formed. The titanium nitride layer is chemically removed. Ions with or without a dopant are then implanted into the cobalt silicide layer. During the ion implantation, at least a portion of the cobalt silicide layer is transformed into an amorphous cobalt silicon mixture while the non-amorphous portion remains single crystal. If the ion implantation contains dopants, then after the implantation is completed, both the amorphous and non-amorphous portions of the cobalt silicide layer contain the dopants. The substrate is then annealed in either an ambient comprising a nitrogen gas or in an oxidizing ambient. During the anneal, the amorphous portion of the silicon substrate recrystallizes into a single crystal cobalt silicide layer. If the cobalt silicide layer after the ion implantation contain dopants, then during the anneal the dopants are driven out of the cobalt silicide layer and diffuse into the silicon substrate to form a conformal shallow junction. The resulting structure can be used in the vertical integration of microelectronic devices. In other words, the resulting structure is suitable for growing selective epitaxial silicon, for growing epitaxial insulators, for processing devices above the silicide in that epitaxial silicon, and for processing devices with buried conductors.

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Fremont, CA, United States of America

M Lawrence Dass