Intel Corporation

M Lawrence A Dass

Krishna Seshan

Geoffrey L Bakker

John Magana

Amir Roggel

Kenneth D Karklin

Isaura S Gaeta

A method of passivating an integrated circuit (IC) is provided. An insulating layer is formed onto the IC. An adhesion layer is formed onto a surface of the insulating layer by treating the surface of the insulating layer with a gas. A first passivation layer is formed upon the adhesion layer, the first passivation layer and the gas including at least one common chemical element.

Semiconductor passivation deposition process for interfacial adhesion

A method of manufacturing liquid crystal devices on a silicon substrate is disclosed. Such a method is accomplished by preparing a silicon substrate having a plurality of die arranged in an array with scribe streets between the dies, and alignment marks within designated scribe streets; preparing a glass substrate having scribe lines, alignment marks within designated scribe lines and openings for filing liquid crystal; attaching the glass substrate to the silicon substrate using the alignment marks on the glass substrate and on the silicon substrate to form a silicon-glass assembly; filling liquid crystal, via the openings on the glass substrate, into a cell gap of each die on the silicon-glass assembly, and sealing the openings on each die to form a liquid crystal device; and separating liquid crystal devices from the silicon-glass assembly along the scribe lines on the glass substrate.

Wafer level electro-optical sort testing and wafer level assembly of micro liquid crystal-on silicon (LCOS) devices

A method of exposing a bond pad includes: providing an integrated circuit having a bond pad, a first passivation layer overlying an area portion of the bond pad, and a second passivation layer overlying the first passivation layer; removing a portion of the second passivation layer above the area portion of the bond pad exposing an area of the first passivation layer; curing the second passivation; and etching a portion of the exposed area of the first passivation layer to expose the top surface of the bond pad. A method of coupling an integrated circuit chip to a chip package is also disclosed as is a method of probing the bond pads of an integrated circuit. A probe card is further disclosed, including a probe assembly coupled to a printed circuit board, the probe assembly having a sloped sidewall portion with a plurality of probing beams extending from the sidewall portion.

Integrated passivation process, probe geometry and probing process

A wafer cutting apparatus which includes a wafer saw, a detector, and a control unit. The detector detects a variable of a wafer being sawed. The control unit utilizes the variable to control the saw.

Method and apparatus for cutting a wafer

A method of passivating an integrated circuit (IC) is provided. An insulating layer is formed onto the IC. An adhesion layer is formed onto a surface of the insulating layer by treating the surface of the insulating layer with a gas and gas plasma. A first passivation layer is formed upon the adhesion layer, the first passivation layer and the gas and gas plasma including at least one common chemical element.

Growing community of inventors

Fremont, CA, United States of America

M Lawrence A Dass