Vishay-siliconix

M Ayman Shibib

Kyle Terrill

Wenjie Zhang

Misbah Ul Azam

Jun Hu

Sanjay Havanur

Chanho Park

Semiconductor device with multiple independent gates. A gate-controlled semiconductor device includes a first plurality of cells of the semiconductor device configured to be controlled by a primary gate, and a second plurality of cells of the semiconductor device configured to be controlled by an auxiliary gate. The primary gate is electrically isolated from the auxiliary gate, and sources and drains of the semiconductor device are electrically coupled in parallel. The first and second pluralities of cells may be substantially identical in structure.

Semiconductor device with multiple independent gates

A vertical trench shield device can include a plurality of gate structures and a termination structure surrounding the plurality of gate structures. The plurality of gate structures can include a plurality of gate regions and a corresponding plurality of gate shield regions. The plurality of gate structures can be disposed between the plurality of source regions, and extending through the plurality of body regions to the drift region. The plurality of gate structures can be separated from each other by a first predetermined spacing in a core area. A first set of the plurality of gate structures can extend fully to the termination structure. The ends of a second set of the plurality of gate structures can be separated from the termination structure by a second predetermined spacing. The first and second spacings can be configured to balance charge in the core area and the termination area in a reverse bias condition.

Methods of manufacture of termination for vertical trench shielded devices

A method of fabricating semiconductor devices including epitaxially depositing a heavily doped substrate layer that is substantially free of crystalline defects on a lightly doped virtual substrate. The device regions of the semiconductor devices can be fabricated about the heavily doped substrate layer before the lightly doped virtual substrate is removed.

Virtual wafer techniques for fabricating semiconductor devices

A transistor and method of manufacturing an electrically active chip seal ring surrounding the gate, gate insulator and source structure of the active core area of the transistor. The chip seal ring can be electrically coupled to the gate to seal the active core area from intrusions of contaminants, impurities, defects and or the like.

Transistors with electrically active chip seal ring and methods of manufacture

Split gate semiconductor with non-uniform trench oxide. A metal oxide semiconductor field effect transistor (MOSFET) comprises a plurality of parallel trenches. Each such trench comprises a first electrode coupled to a gate terminal of the MOSFET and a second electrode, physically and electrically isolated from the first electrode. The second electrode is beneath the first electrode in the trench. The second electrode includes at least two different widths at different depths below a primary surface of the MOSFET. The trenches may be formed in an epitaxial layer. The epitaxial layer may have a non-uniform doping profile with respect to depth below a primary surface of the MOSFET. The second electrode may be electrically coupled to a source terminal of the MOSFET.

Split gate semiconductor with non-uniform trench oxide

Vertical sense devices in vertical trench MOSFET. In accordance with an embodiment of the present invention, an electronic circuit includes a vertical trench metal oxide semiconductor field effect transistor configured for switching currents of at least one amp and a current sensing field effect transistor configured to provide an indication of drain to source current of the MOSFET. A current sense ratio of the current sensing FET is at least 15 thousand and may be greater than 29 thousand.

Vertical sense devices in vertical trench MOSFET

Termination for vertical trench shielded devices

Vertical sense devices in vertical trench MOSFET. In accordance with an embodiment of the present invention, a semiconductor device includes a main vertical trench metal oxide semiconductor field effect transistor (main-MOSFET). The main-MOSFET includes a plurality of parallel main trenches, wherein the main trenches comprise a first electrode coupled to a gate of the main-MOSFET, and a plurality of main mesas between the main trenches, wherein the main mesas comprise a main source and a main body of the main-MOSFET. The semiconductor device also includes a sense-diode. The sense-diode includes a plurality of sense-diode trenches, wherein each of the sense-diode trenches comprises a portion of one of the main trenches, and a plurality of sense-diode mesas between the source-FET trenches, wherein the sense-diode mesas comprise a sense-diode anode that is electrically isolated from the main source of the main-MOSFET.

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San Jose, CA, United States of America

M Ayman Shibib