Arm Limited

Mélanie Emanuelle Lucie Teyssier

David Michael Bull

Frederic Claude Marie Piry

Nicolas Chaussade

Florent Begon

Luca Scalabrino

Guillaume Schon

Rémi Marius Teyssier

Jocelyn Francois Orion Jaubert

Albin Pierick Tonnerre

Philippe Pierre Maurice Luc

A data processing apparatus executes instructions in a sequence of pipelined execution stages. An error detection unit twice samples a signal associated with execution of an instruction and generates an error signal if the samples differ. An exception storage unit maintains an age-ordered list of entries corresponding to instructions issued to the execution pipeline and can mark an entry to show if the error signal has been generated in association with that instruction. A timer unit is responsive to generation of the error signal to initiate timing of a predetermined time period. An error recovery unit initiates a soft pipeline flush procedure if an oldest pending entry in the list has said error marker stored in association therewith and initiates a hard pipeline flush procedure if said predetermined time period elapses, said hard flush procedure comprising resetting said pipeline to a predetermined state.

Error recovery upon reaching oldest instruction marked with error or upon timed expiration by flushing instructions in pipeline pending queue and restarting execution

A load store pipelineincludes an issue queueand load store circuitry. The load store circuitryincludes the plurality of access slot circuitsto. Dependency tracking circuitryserves to track a freeable number of access slot circuitstocorresponding to the sum of access slot circuits that are empty and those processing data access instructions which have not bypassed any preceding data access instructions within the program execution order.

Resource management within a load store unit

A data processing apparatus and method of data processing are provided. The data processing apparatus comprises execution circuitry configured to execute a sequence of program instructions. Checkpoint circuitry is configured to identify an instance of a predetermined type of instruction in the sequence of program instructions and to store checkpoint information associated with that instance. The checkpoint information identifies a state of the data processing apparatus prior to execution of that instance of the predetermined type of instruction, wherein the predetermined type of instruction has an expected long completion latency. If the execution circuitry does not complete execution of that instance of the predetermined type of instruction due to occurrence of a predetermined event, the data processing apparatus is arranged to reinstate the state of the data processing apparatus with reference to the checkpoint information, such that the execution circuitry is then configured to recommence execution of the sequence of program instructions at that instance of the predetermined type of instruction.

Checkpointing long latency instruction as fake branch in branch prediction mechanism

Growing community of inventors

Grasse, France

Mélanie Emanuelle Lucie Teyssier