Airbus Defence and Space Sas

Lyonel Barthe

Benjamin Gadat

Thibault Maisonnat

Arnaud Collin

Jean-Frédéric Chouteau

A symbol time synchronization device with parallel architecture is disclosed having a sample storage and reordering module including a control unit and 2×P cyclically ordered FIFOs, an interpolation module configured to supply, at each clock stroke, a time error indication (Err-Ind) taking one of the values 'Nominal', “Underrun” or “Overrun”, at a current clock stroke, the control unit is configured to write a sample to each of P successive FIFOs, read a sample from each of P, P−1, or P+1 successive FIFOs depending on whether the time error indication (Err-Ind) is respectively “nominal”, “underrun” or “overrun”, reorder samples to be supplied to the interpolation module using a permutation network.

Device and method for synchronizing symbol time with parallel architecture

The disclosure relates to an LDPC decoding method which involves performing iterations until a stop criterion is satisfied. Each iteration involves calculating variable messages (α), calculating parity check messages (β), and calculating a posteriori estimation variables. The parity check messages (β) and the posteriori estimation variables (γn) being saturated at a predetermined maximum value. At the end of an iteration, when the number of saturations reaches a specified threshold, the method involves at least a first scaling of the parity check messages (β) and the a posteriori estimation variables (γ). Scaling corresponds to assigning, to a value, an integer which has the same sign and whose absolute value is the nearest integer greater than the absolute value of the value divided by two.

Adaptive scaling of parity check messages for LDPC decoding

An LDPC decoding method is disclosed in which the LDPC code is defined by a parity matrix having a layered structure, and the method involves performing iterations until a stop criterion is satisfied. Each iteration involves the successive processing of the different layers. Processing a layer involves calculating variable messages (a), calculating parity check messages, calculating a posteriori estimation variables (γ), and calculating a partial syndrome. The evaluation of the stop criterion involves checking if, for a plurality of successive iterations, the number of iterations for which all the partial syndromes are zero, from which the number of iterations for which at least one of the partial syndromes is non-zero is subtracted, is greater than or equal to a predetermined stop threshold.

Stop criterion for decoding an LDPC code

The disclosure relates to an LDPC decoding method which involves performing iterations until a stop criterion is satisfied. Each iteration involves computing variable messages (α), computing parity check messages (β), and computing a posteriori estimation variables. Computing a parity check message (β) for a parity check node (CN) involves determining the two smallest values (Mini1, Min2) among the absolute values of the variable messages associated with the parity check node (CN), comparing a difference between said values with a threshold, determining a correction value according to the result of the comparison, and computing the parity check message according to the correction value.

Optimization of the computation of parity check messages in a min-sum LDPC decoding method

A data encoding device suitable for encoding a plurality of LDPC codes is disclosed including an input interface and an output interface, and a first circuit for encoding quasi-cyclic LDPC code, connected at an input to the input interface and at an output to the input of a first multiplexer circuit, a second circuit for encoding quasi-cyclic LDPC code, connected at an input to the input interface and at an output to the input of the first multiplexer circuit, a third circuit for encoding quasi-cyclic LDPC code, connected at an input to the output of the first multiplexer circuit and at an output to the input of a second multiplexer circuit.

Device and method for efficiently encoding quasi-cyclic LDPC codes

A method and a receiver device for detecting the start of a frame of a satellite communication signal. A shaping filtering is applied directly after sampling of the signal, before a frequency correction is applied. During a first phase, an approximate frequency error and a candidate first sample for the start of the frame are estimated by performing several correlations respectively associated with different frequency hypotheses. The samples obtained after sampling or after shaping filtering are buffered during the execution of the first phase. Then, during a second phase, a final candidate sample for the start of the frame is determined from the memorised samples, using the approximate frequency error and the candidate first sample estimated during the first phase.

Method and receiver device for detecting the start of a frame of a satellite communications signal

A method for detecting useful signals in an overall signal. Each useful signal may be affected with a frequency drift. In the detection phase, frequency spectra for detecting the overall signal for multiple detection time windows are calculated and useful signals according to the detection frequency spectra are detected. In the estimation phase, for each useful signal detected: the frequency of the overall signal for multiple frequency drift values is reset. In the estimation phase, for each useful signal detected, a frequency spectrum is calculated for the estimation of the overall signal for each frequency drift value over an estimation time window having the useful signal detected and of a duration higher than the detection time window. In the estimation phase, for each useful signal detected, the frequency drift is estimated affecting the useful signal detected according to the estimation frequency spectra.

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Toulouse, France

Lyonel Barthe