International Business Machines Corporation

Lynne Marie Gignac

Yun-Yu Wang

Chao-Kun Hu

Horatio Seymour Wildman

Chih-Chao Yang

Cyril Cabral, Jr

Kenneth Parker Rodbell

Kwong Hon Wong

Anthony Gene Domenicucci

Ping-Chuan Wang

Conal Eugene Murray

Panayotis Constantinou Andricacos

Kaushik Chanda

Oliver C Wells

Cyprian Emeka Uzoh

Christian Lavoie

Wai-Kin Li

John Michael Cotte

Thomas M Shaw

Vincent James McGahay

Roy Arthur Carruthers

Hazara Singh Rathore

Patrick William Dehaven

Glen L Miles

Wilma Jean Horkans

Peter Stevens Locke

Ronald Gene Filippi, Jr

Prabhat Tiwari

Surbhi Mittal

Lawrence Alfred Clevenger

Jeffrey P Gambino

Sampath Purushothaman

Timothy Joseph Dalton

Kirk David Peterson

Stephen McConnell Gates

Sandra Guy Malhotra

Ronald G Filippi

John Anthony Fitzsimmons

Damon B Farmer

Stephen Mark Rossnagel

Franco Stellari

Paul Charles Jamison

Robert L Bruce

Sebastian Ulrich Engelmann

Kang-Wook Lee

Darryl D Restaino

Stephan Alan Cohen

Abram L Falk

Eric Gerhard Liniger

John A Miller

Roy Charles Iggulden

John Bruley

Tina Jane Wagner

Chung-Ching Lin

Rainer Florian Schnabel

Eva Erika Simonyi

Stefan Weber

Keith K Wong

Patricia A O'Neil

Chung-Ping Eng

Jonathan Rullan

Thitima Suwannasiri

Wai-Kin Ll

Ping-Chaun Wang

Luxherta Buzi

A process of improving a profile and repairing sidewall damage for phase change memory devices. The process includes applying inert ion beam etching to trim a sidewall of a layer of phase change memory material in a phase change memory device, where the sidewall has been damaged in reactive ion etching using halogens. In the process, the inert ion beam etching is with low energy. In the process, applying the inert ion beam etching to trim the sidewall is at a predetermined low temperature. In the process, applying the inert ion beam etching to trim the sidewall is at a predetermined small angle between an inert ion beam and a surface tangent of the sidewall.

Applying inert ion beam etching for improving a profile and repairing sidewall damage for phase change memory devices

A membrane is electrically charged to a polarity. A surface of carbon nanotubes (CNTs) in a solution is caused to acquire a charge of the polarity. The solution is filtered through the membrane. An electromagnetic repulsion between the membrane of the polarity and the CNTs of the polarity causes the CNTs to spontaneously align to form a crystalline structure.

Crystalline film of carbon nanotubes

One or more contacts are detected in an electron microscope image corresponding to a region of interest on an integrated circuit. One or more standard cells are identified based on the detected one or more contacts in the electron microscope image. One or more components of the integrated circuit are determined based on the identified one or more standard cells.

Non-destructive determination of components of integrated circuits

A method of fabricating an interconnect structure is provided which includes providing a dielectric material having a dielectric constant of about 3.0 or less and at least one conductive material embedded therein, the at least one conductive material has an upper surface that is coplanar with an upper surface of the dielectric material; and forming a noble metal-containing cap directly on the upper surface of the at least one conductive material, wherein the noble metal cap is discontinuous or non-uniform.

Discontinuous/non-uniform metal cap structure and process for interconnect integration

An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire.

System involving electrically reprogrammable fuses

An interconnect structure including a noble metal-containing cap that is present at least on some portion of an upper surface of at least one conductive material that is embedded within an interconnect dielectric material is provided. In one embodiment, the noble metal-containing cap is discontinuous, e.g., exists as nuclei or islands on the surface of the at least one conductive material. In another embodiment, the noble metal-containing cap has a non-uniform thickness across the surface of the at least one conductive material.

Methods and systems involving electrically reprogrammable fuses

A semiconductor structure including a highly reliable high aspect ratio contact structure in which key-hole seam formation is eliminated is provided. The key-hole seam formation is eliminated in the present invention by providing a densified noble metal-containing liner within a high aspect ratio contact opening that is present in a dielectric material. The densified noble metal-containing liner is located atop a diffusion barrier and both those elements separate the conductive material of the inventive contact structure from a conductive material of an underlying semiconductor structure. The densified noble metal-containing liner of the present invention is formed by deposition of a noble metal-containing material having a first resistivity and subjecting the deposited noble metal-containing material to a densification treatment process (either thermal or plasma) that decreases the resistivity of the deposited noble metal-containing material to a lower resistivity.

Structure and process for conductive contact integration

A semiconductor structure is provided that includes an interconnect structure and a fuse structure located in different areas, yet within the same interconnect level. The interconnect structure has high electromigration resistance, while the fuse structure has a lower electromigration resistance as compared with the interconnect structure. The fuse structure includes a conductive material embedded within an interconnect dielectric in which the upper surface of the conductive material has a high concentration of oxygen present therein. A dielectric capping layer is located atop the dielectric material and the conductive material. The presence of the surface oxide layer at the interface between the conductive material and the dielectric capping layer degrades the adhesion between the conductive material and the dielectric capping layer. As such, when current is provided to the fuse structure electromigration of the conductive material occurs and over time an opening is formed in the conductive material blowing the fuse element.

Efficient interconnect structure for electrical fuse applications

A magnetically focused scanning charged particle microscope having an array detector placed to detect scattered particles, wherein the particles fall substantially non-tangentially to the surface of the array detector.

Method for SEM measurement of features using magnetically filtered low loss electron microscopy

A device, system and method for evaluating reliability of a semiconductor chip are disclosed. Strain is determined at a location of interest in a structure. Failures are evaluated in a plurality of the structures after stress cycling to determine a strain threshold with respect to a feature characteristic. Structures on a chip or chips are evaluated based on the feature characteristic to predict reliability based on the strain threshold and the feature characteristic. Predictions and design changes may be made based on the results.

Control of liner thickness for improving thermal cycle reliability

Disclosed is a procedure to coat the free surface of Cu damascene lines by a 1-5 nm thick element prior to deposition of the inter-level dielectric or dielectric diffusion barrier layer. The coating provides protection against oxidation, increases the adhesion strength between the Cu and dielectric, and reduces interface diffusion of Cu. In addition, the thin cap layer further increases electromigration Cu lifetime and reduces the stress induced voiding. The selective elements can be directly deposited onto the Cu embedded within the under layer dielectric without causing an electric short circuit between the Cu lines. These chosen elements are based on their high negative reduction potentials with oxygen and water, and a low solubility in and formation of compounds with Cu.

On-chip Cu interconnection using 1 to 5 nm thick metal cap

An imaging device having many detector elements is used to construct multiple images of the surface of a specimen in a scanning electron microscope (SEM) using signals from different elements of the imaging device as the specimen is scanned a single time in the SEM.

Method of forming images in a scanning electron microscope

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Beacon, NY, United States of America

Lynne Marie Gignac